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Original question:
hello, ti expert:
The sdk version we use is 0703, and now we encounter a DDR problem. We use Micron’s LPDDR4 chip, the model is MT53D1024M32D4DT-046 AAT.The power-on and power-off test of the switch machine has always been very stable. Now there is a demand that a simple reset of the TDA4 chip can also achieve a stable restart. Now the problem arises here. On the MCU side, the reset is implemented through the MCU_PORz pin, TDA4 reset without close power, and it is found that lpddr4 will fail to initialize. Tested hundreds of times, occasionally a few times, the frequency is also very high. Stuck in the Board_DDRChangeFreqAck function, has been blocked in HW_RD_REG32(BOARD_DDR_FSP_CLKCHNG_REQ_ADDR) & 0x80 here, as shown in the picture below
We now implement reset by pulling down MCU_PORz, the datasheet is explained as follows
I saw that there is an api that can also implement reset. What is the difference between the following api and the above direct control pin?
Sciclient_pmDeviceReset(SCICLIENT_SERVICE_WAIT_FOREVER);
Regarding this problem, I found a lot of similar problems on E2E, the following link generally means that it can be solved by changing the configuration, and the configuration file has a newer version
The following problem is solved by frequency reduction. We require DDR4 to run at the highest bandwidth of 2133 clock, 4266Mb/s
e2e.ti.com/.../tda4vm-ddr-init-failed-in-sbl
This is 4266Mb/s E2E, but no one replied
e2e.ti.com/.../tda4vm-ddr-at-4266-init-failed
