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Original question:
[FAQ] AM64X/AM62X: How do I route the same GPIO bank interrupts to different destination cores?
Dear TI team,
I consulted the FAQ regarding pin-based interrupt rather than bank-based. I don't know whether i can post question in the FAQ threads. In the provided example code '6472.empty_am64x-evm_r5fss0-0_freertos_ti-arm-clang.zip,' I observed the use of the 'GPIO_bankIntrEnable' function, and the callback function appears to be associated with bank interrupt. For pin interrupt, should we adhere to the same approach? I couldn't find any function to enable a single pin interrupt analogous to 'GPIO_bankIntrEnable.' Your guidance on this matter would be appreciated.
Additionally, is there a plan to include support for the pin interrupt feature in sysconfig in the roadmap?
Thank you
Chris
Hello Chris,
You can't raise questions in the FAQ, and it mostly got locked state.
For new queries, you have to raise new threads.
Currently, syssfg is not supporting pin interrupts , and I don't have an idea when we will support it in the MCU+SDK, but I can check with the development team on this. Thanks for your input.
Coming to your question AM64X can support both bank interrupts and pin interrupts.
For pin interrupts, you just have to add the pin number in the highlighted line, and except for that, there is no difference.
There are few FAQs on GPIO, so please go through them.
Regards,
S.Anil.
