DDR0 and DDR1 register access SYS/BIOS for TI814

Hi Niklas --

The BIOS Cache_wait API does a dummy write/read to one the first reserved register in this region to ensure that the memory system has been updated prior to returning from wait.   Cache_wbInv(), wb, inv, call Cache_wait() internally.   Problem is that the cache counter can reach zero before the memory system has been completely updated.  The wb is still in the busses outside the device.  The write/read of this configuration register will stall until the memory system is up to date.

Below is the code snip from Cache.c which you can find in your <biosinstalldir>/packages/ti/sysbios/family/c64p/Cache.c file.

-Karl-

/*
 *  ======== Cache_wait ========
 *  Wait for the L2 count to complete.  This function needs only to wait
 *  for L2 word count since all block cache operations in BIOS are done
 *  through the L2 registers and all global cache operations must already
 *  wait until the operation completes.  Note:  Its sufficient to wait
 *  on one of the L2 count registers since all 3 count registers are
 *  mirrors of one another and map to the same bits.
 */
Void Cache_wait()
{
    UInt mask;

    /* wait for L2 word count to be zero */
    while (*L2WWC != 0) {
        ;
    }

    /*
     *  make a dummy write and read to emif config register to
     *  insure that data made it out to external memory, otherwise
     *  its possible that the data is out of the Master's view but
     *  has not reached its final destination.
     */
    mask = Hwi_disable();
    if (Cache_module->emifAddr != NULL) {
        *(Cache_module->emifAddr) = 0;
        *(Cache_module->emifAddr);
        Cache_module->emifAddr = NULL;
    }
    Hwi_restore(mask);
}