• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 97 subscribers
  • Views 840 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Composite Video on Beagle Board using OMAP35x-PSP-SDK-02.01.01.08

Kiran Murari
Prodigy 20 points
Other Parts Discussed in Thread: SYSCONFIG

Hi All,

I trying to get Composite Video working on Beagle Board. I am using OMAP35x-PSP-SDK-02.01.01.08, which has the DSS2 patches.

When I tried executing the instructions present in the DSS documentation (Clone GFX overlay to LCD and TV), I am able to get S-Video output. But unable to get Composite Video working.

The only change that I have done between S-Video and Composite Video is change the default VENC type from OMAP_DSS_VENC_TYPE_SVIDEO to OMAP_DSS_VENC_TYPE_COMPOSITE in arch/arm/mach-omap2/board-omap3beagle.c

As I started debugging the code, I see that all the settings are getting reflected properly. The resolution is set to 720 * 472, venc type is OMAP_DSS_VENC_TYPE_COMPOSITE, dispc_go function in arch/arm/plat-omap/dss/dispc.c is being called with omap channel set to OMAP_DSS_CHANNEL_DIGIT.

But in the function dispc_go (arch/arm/plat-omap/dispc.c): I always hit with "if the channel is not enabled, we don't need GO" condition and comes out of the function. The corresponding code snippet is as follows:

*********************** CODE START ***********************
    if (channel == OMAP_DSS_CHANNEL_LCD) {
        bit = 0; /* LCDENABLE */
    }
    else {
        bit = 1; /* DIGITALENABLE */
    }

    /* if the channel is not enabled, we don't need GO */
    if (REG_GET(DISPC_CONTROL, bit, bit) == 0) {
        goto end;
    }

    if (channel == OMAP_DSS_CHANNEL_LCD) {
        bit = 5; /* GOLCD */
    }
    else {
        bit = 6; /* GODIGIT */
    }
*********************** CODE END ***********************

Further debugging, I see that in the function initialize_overalys (arch/arm/plat-omap/dss/display.c): overlay for TV manager is macro protected with CONFIG_VID1_TV_MANAGER and CONFIG_VID2_TV_MANAGER. I tried to enable this macro, but could not find a kernel config option pertaining to this, so I have put a #define CONFIG_VID1_TV_MANAGER before this. Below is the code snippet.

*********************** CODE START ***********************   

/* Set the TV MGR as the default mgr for video based on config option */
#define CONFIG_VID1_TV_MANAGER /* Defined explicitly */
#ifdef CONFIG_VID1_TV_MANAGER
    ovl = omap_dss_get_overlay(1);
    omap_dss_unset_manager(ovl);
    omap_dss_set_manager(ovl, tv_mgr);
#endif
#ifdef CONFIG_VID2_TV_MANAGER
    ovl = omap_dss_get_overlay(2);
    omap_dss_unset_manager(ovl);
    omap_dss_set_manager(ovl, tv_mgr);
#endif

*********************** CODE END ***********************

The reason to do this is, in the DSS documentation the "Clone GFX overlay to LCD and TV" script uses vid1. But still I am unable get Composite Video working.

Appreciate any help in this regard.

Regards,

Kiran Murari

  • 0
    Prodigy 20 points

    Hello All,
    After trying out things on how to enable the VID1 TV Manager, I figured out that the "Video for Linux" is not enabled in the kernel.
    I enabled Video for Linux and in "Video capture adapters" I could see the VID1 Overlay Manager and VID2 Overlay Manager.
    I have set VID1 Overlay Manger to "Use TV Manager" and VID2 Overlay Manager to "Use LCD Manager".
    Now executed the "Clone GFX overlay to LCD and TV" script. But still no luck in getting Composite Video working.

    I did a register dump and I see that DISPC_CONTROL register holds the value 0x1830B. Mapping this to the available bits,
    both GODIGITAL and GOLCD are "0".
    Couldn't figure out how to enable them.

    Any thoughts?

    Regards,
    Kiran Murari

  • 0 in reply to Kiran Murari
    Prodigy 30 points

    Hi Kiran,

     

    Can you please share me the code for DSS initialization for either mode, composit or s-video.

    Actualy i am porting a driver for s-video for BeagleBoard and facing some problems. After initializing DSS, VENC and DISPC the only backgroud color of the screen changed and i am unable to dislapy the data from fram buffer to the LCD(in TV output mode). Below is my initialization sequence

    *((uint *) 0x48310034) = 0xfefffedf;//GPIO_OE  

          *((uint *) 0x48310094) = 0x01000120;//GPIO_SETDATAOUT            

          *((uint *) 0x48004D44) = 0x0001b00c;//CM_CLKSEL2_PLL                                  

          *((uint *) 0x48004E40) = 0x00001006;//CM_CLKSEL_DSS                                                               

          *((uint *) 0x48004D00) = 0x00370037;//CM_CLKEN_PLL

          *((uint *) 0x48004E00) = 0x00000007;//CM_FCLKEN_DSS

          *((uint *) 0x48004E10) = 0x00000001;//CM_ICLKEN_DSS

         

          *((uint *) 0x48050010) = 0x00000001;//DSS_SYSCONFIG

          *((uint *) 0x48050040) = 0x00000078;//DSS_CONTROL

          *((uint *) 0x48050044) = 0x00000000;//DSS_SDI_CONTROL

          *((uint *) 0x48050048) = 0x00000000;//DSS_PLL_CONTROL

         

          *((uint *) 0x48050C00) = 0x00000002;//Video Encoder base address

          *((uint *) 0x48050C08) = 0x00000000;//VENC_F_CONTROL

          *((uint *) 0x48050C10) = 0x00000001;//VENC_VIDOUT_CTRL

          *((uint *) 0x48050C14) = 0x00008040;//VENC_SYNC_CTRL

          *((uint *) 0x48050C1C) = 0x00000359;//VENC_LLEN

          *((uint *) 0x48050C20) = 0x0000020C;//VENC_FLENS

          *((uint *) 0x48050C24) = 0x00000000;//VENC_HFLTR_CTRL

          *((uint *) 0x48050C28) = 0x043F2631;//VENC_CC_CARR_WSS_CARR

          *((uint *) 0x48050C2C) = 0x00000000;//VENC_C_PHASE

          *((uint *) 0x48050C30) = 0x00000102;//VENC_GAIN_U

          *((uint *) 0x48050C34) = 0x0000016C;//VENC_GAIN_V

          *((uint *) 0x48050C38) = 0x0000012F;//VENC_GAIN_Y

          *((uint *) 0x48050C3C) = 0x00000043;//VENC_BLACK_LEVEL

          *((uint *) 0x48050C40) = 0x00000038;//VENC_BLANK_LEVEL

          *((uint *) 0x48050C44) = 0x00000007;//VENC_X_COLOR

          *((uint *) 0x48050C48) = 0x00000001;//VENC_M_CONTROL

          *((uint *) 0x48050C4C) = 0x00000038;//VENC_BSTAMP_WSS_DATA

          *((uint *) 0x48050C50) = 0x21F07C1F;//VENC_S_CARR

          *((uint *) 0x48050C54) = 0x0000F003;//VENC_LINE21

          *((uint *) 0x48050C58) = 0x01310011;//VENC_LN_SEL

          *((uint *) 0x48050C5C) = 0x0000F003;//VENC_L21_WC_CTL

          *((uint *) 0x48050C60) = 0x00000000;//VENC_HTRIGGER_VTRIGGER

          *((uint *) 0x48050C64) = 0x069300F4;//VENC_SAVID_EAVID

          *((uint *) 0x48050C68) = 0x0016020C;//VENC_FLEN_FAL

          *((uint *) 0x48050C6C) = 0x00060107;//VENC_LAL_PHASE_RESET

          *((uint *) 0x48050C70) = 0x008E0350;//VENC_HS_INT_START_STOP_X

          *((uint *) 0x48050C74) = 0x000F0359;//VENC_HS_EXT_START_STOP_X

          *((uint *) 0x48050C78) = 0x01A00000;//VENC_VS_INT_START_X

          *((uint *) 0x48050C7C) = 0x020701A0;//VENC_VS_INT_STOP_X_VS_INT_START_Y

          *((uint *) 0x48050C80) = 0x01AC0024;//VENC_VS_INT_STOP_Y_VS_EXT_START_X

          *((uint *) 0x48050C84) = 0x020D01AC;//VENC_VS_EXT_STOP_X_VS_EXT_START_Y

          *((uint *) 0x48050C88) = 0x00000006;//VENC_VS_EXT_STOP_Y

          *((uint *) 0x48050C90) = 0x03480078;//VENC_AVID_START_STOP_X

          *((uint *) 0x48050C94) = 0x02060024;//VENC_AVID_START_STOP_Y

          *((uint *) 0x48050CA0) = 0x0001008A;//VENC_FID_INT_START_X_FID_INT_START_Y

          *((uint *) 0x48050CA4) = 0x01AC0106;//VENC_FID_INT_OFFSET_Y_FID_EXT_START_X

          *((uint *) 0x48050CA8) = 0x01060006;//VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y

          *((uint *) 0x48050CB0) = 0x00140001;//VENC_TVDETGP_INT_START_STOP_X

          *((uint *) 0x48050CB4) = 0x00010001;//VENC_TVDETGP_INT_START_STOP_Y

          *((uint *) 0x48050CB8) = 0x00F90000;//VENC_GEN_CTRL

          *((uint *) 0x48050CC4) = 0x0000000D;//VENC_OUTPUT_CONTROL

          *((uint *) 0x48050CC8) = 0x00000000;//VENC_OUTPUT_TEST

               

          *((uint *) 0x48050410) = 0x00002015;//DISPC_SYSCONFIG

          *((uint *) 0x48050414) = 0x00000001;//DISPC_SYSSTATUS

          *((uint *) 0x48050444) = 0x00000004;//DISPC_CONFIG   

          *((uint *) 0x48050450) = 0x0000FFFF;//DISPC_DEFAULT_COLORm

          *((uint *) 0x48050454) = 0x00000000;//DISPC_TRANS_COLORm

          *((uint *) 0x48050478) = 0x00770167;//DISPC_SIZE_DIG

          *((uint *) 0x48050418) = 0x0001FFFF;//DISPC_IRQSTATUS

          *((uint *) 0x4805041C) = 0x0001FFFF;//DISPC_IRQENABLE

     

          *((uint *) 0x48050480) = frame_buf;//DISPC_GFX_BA0

          *((uint *) 0x48050484) = frame_buf + 0x5A1;//DISPC_GFX_BA1 Frame is 720x480.The offset is (720*2)+1

          *((uint *) 0x48050488) = 0x00000000;//DISPC_GFX_POSITION

          *((uint *) 0x4805048c) = 0x02cf04ff;//DISPC_GFX_SIZE

          *((uint *) 0x480504a0) = 0x00000093;//DISPC_GFX_ATTRIBUTES

          *((uint *) 0x480504a8) = 0x00000400;//DISPC_GFX_FIFO_SIZE_STATUS

          *((uint *) 0x480504a4) = 0x03FC03BC;//DISPC_GFX_FIFO_THRESHOLD

          *((uint *) 0x480504ac) = 0x00000001;//DISPC_GFX_ROW_INC

          *((uint *) 0x480504b0) = 0x00000001;//DISPC_GFX_PIXEL_INC

          *((uint *) 0x480504b4) = 0x00000000;//DISPC_GFX_WINDOW_SKIP

          *((uint *) 0x480504b8) = 0x807ff000;//DISPC_GFX_TABLE_BA

                     

          NU_Sleep(500);

         

          *((uint *) 0x48050440) = 0x80B834A;//DISPC_CONTROL

      

          NU_Sleep(500);

      

          *((uint *) 0x48050440) = 0x80B834A;//DISPC_CONTROL