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Frequent questions

  • [FAQ] PROCESSOR-SDK-AM64X: Licensing of industrial protocols provide in MCU-SDK

    Part Number: PROCESSOR-SDK-AM64X Hi, What is the "TI Commercial" licensing process for Industrial Protocols provided in MCU-SDK package ? Regards

  • [FAQ] PROCESSOR-SDK-AM64X: Flash Programming Options in Mass Production Phase

    Part Number: PROCESSOR-SDK-AM64X Hi, What is the recommended production method of loading in flash device during mass production? Regards

  • [FAQ] AM64X : How to Reset (Warm Reset ) the SOC from Software ?

    Part Number: AM6442 Hello TI experts, I want to make the SOC reset from software. How can I do it? What is the difference between POR (power on reset) and warm reset? This FAQ mainly explains how to Reset the SOC. And what are the registers used…

  • [FAQ] PROCESSOR-SDK-J721E: How to use TR for transfers in McSPI, instead of packet descriptors?

    Part Number: PROCESSOR-SDK-J721E By default, McSPI/SPI Drivers in PSDKRA uses packet descriptors for transferring or for receiving data to/from the SPI slave device. Sometimes it might require to use TR descriptors, because TR supports additional functionalities…

  • [FAQ] AM62A7-Q1: how to connect the pin net VDDSHV4, VDDSHV5, and VDDSHV6 if SD card is not used

    Part Number: AM62A7-Q1 SD cards is not need in our project using AM62A7-Q1. if SD card is not used, how to connect the pin net VDDSHV4, VDDSHV5, and VDDSHV6 of AM62A7-Q1? leave it open or connected directly to VSS or ?

  • [FAQ] EDGE-AI-STUDIO: Edge AI Resources for AM6xA SoCs

    Part Number: EDGE-AI-STUDIO Texas Instruments has a multitude of resources available for machine learning at the edge (Edge AI). These are spread across ti.com, dev.ti.com (TI Developer Zone + Edge AI Studio), and github. The majority of these resources…

  • [FAQ] PROCESSOR-SDK-AM64X: Accessing DDR from PRU-ICSSG

    Part Number: PROCESSOR-SDK-AM64X Other Parts Discussed in Thread: SYSCONFIG Hi, Can you please help me to access DDR from a PRU core? . The information in this FAQ applies to all Sitara processors with a PRU_ICSSG: AM24x, AM64x, AM65x. The example…

  • [FAQ] Automate the process of code execution through CCS

    Hi, For running a executable through CCS following steps needs to be performed. Open the Code Composer Studio(CCS). Launch the target configuration file. Load the executable to the desired core. Execute the main() function. To…

  • [FAQ] AM623: Trace impedance requirements for EMMC signals

    Part Number: AM623 Hi, As shown in the screenshot, do the signals connected to eMMC have specific impedance requirements?

  • [FAQ]AM64X : How to Route MCU GPIO Interrupts to MAIN Domain Cores in MCU PLUS SDK Version 6.0 & above ?

    Part Number: AM6442 Other Parts Discussed in Thread: SYSCONFIG I am trying to modify the gpio_input_interrupt example for the R5F0-0 core to work with MCU_GPIO0 pins and run it on the R5 core from the CCS debug session, but for now unsuccessfully. …

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