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Frequent questions

  • [FAQ] TDA4VL: How to resolve NETDEV WATCHDOG: transmit queue timed out issue in Linux (A72) in case of SBL optimized boot flow?

    Part Number: TDA4VL How to resolve NETDEV WATCHDOG: transmit queue timed out issue in Linux (A72) in case of SBL optimized boot flow?

  • [FAQ] J784S4XEVM: MAIN_SPI5 How to test the RX/TX Loop back

    Part Number: J784S4XEVM How to test the RX/TX Loop back for MAIN_SPI5 which is brought out on the J26 header on the EVM?

  • [FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM625SIP Custom board hardware design – Display Parallel Interface (DPI) 24-bit RGB- display interface

    Other Parts Discussed in Thread: AM625 , AM620-Q1 , AM62P , AM62A3 , AM62P-Q1 , AM62A7 , AM62A7-Q1 , AM62A3-Q1 , AM623 Hi TI Experts, I have the below queries regarding the DPII interface We want to use an RGB Display with AM625 Processor. It seems…

  • [FAQ] TDA4VM: SDL BIST Example Application Failing on SDK 8.6

    Part Number: TDA4VM SDL BIST example application halts midway (at the PBIST failure insertion test for Main R5F 1) during execution and fails on SDK 8.6.

  • [FAQ] J721S2XSOMXEVM: How to change DDR frequency for J721E EVM, J721S2 EVM, and J784S4 EVM?

    Part Number: J721S2XSOMXEVM Other Parts Discussed in Thread: TDA4VL The TI SDK supports 4266 MTS by default for J721E/J721S2/J784S4. How can I change the DDR frequency?

  • [FAQ] AM6442: use of 2x RMII EPHY for CPSW

    Part Number: AM6442 Hello, customer wants to use 2x RMII EPHY (DP83826) in slave mode for CPSW. What design/layout challenges does he need to take care? What clock buffer do we recommend to source the common clock for the RMII EPHY and AM64xx? Regards…

  • [FAQ] TDA4VL: How to load kernel , dtb , filesystem from the USB device?

    Part Number: TDA4VL At uboot how we can load the kernel, dtb , filesystem from the USB device on TDA4X EVM ? The detailed procedure is shown below. Boot from eMMC/SD At u-boot Choose one of two possible locations for the root filesystem and…

  • [FAQ] AM623: SDDDR start address 0x0080000000 or 0x0880000000 ?

    Part Number: AM623 Hi, Please give more clarity on the start add of DDR16SS0_SDRAM. In am62x TRM in some places I found like 0x0080000000 and in another place 0x0880000000. in u-boot source code include/configs/am62x_evm.h /* DDR Configuration…

  • [FAQ] PROCESSOR-SDK-J721E: How to use MCU UDMA channels in CSIRX?

    Part Number: PROCESSOR-SDK-J721E Other Parts Discussed in Thread: TDA4VM , SYSCONFIG By default in PSDKRA, CSIRX driver uses Main UDMA channels for storing the output. This article explains how to use MCU UDMA channels in the SDK/vision apps.

  • [FAQ] AM625: How to change device tree to incorporate DDR4 Data pin swaps

    Part Number: AM625 Other Parts Discussed in Thread: SK-AM62 Hello, I am using AM625 SoC and we have swapped some of the data pins within a byte for the DDR0_DQ* for the DDR4. Could you please give us an example on how to change these in the device…

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