Texas Instruments (TI) Processors support forum is an extensive online knowledge base where millions of technical questions and solutions are available 24/7. You can search processors content or ask technical support questions on Sitara™ processors, digital signal processors (DSP) and automotive processors. Find the right solution for your circuit design challenges by using our TI E2E™ support forums that are supported by thousands of contributing TI experts.
Frequent questions

  • [FAQ] AM6x: Yocto build "hangs" for hours with no progress - What's going on?

    (applicable to all TI Sitara and Jacinto devices such as AM62x, AM62Ax, AM64x, AM65x, and so on) Symptoms When doing a Yocto build as per SDK instructions for example of the SDK default image like this... MACHINE=am62xx-evm bitbake -k tisdk-default…

  • [FAQ] AM62A3-Q1: The MISO and MOSI of the SPI

    Part Number: AM62A3-Q1 Hi TI expert, The SOC AM62A define the standard SPI interface by SPI_CS, SPI_CLK, SPI_D0, SPI_D1. If our slave device need to get MISO and MOSI data line, how will we used the D0 and D1 data line. Dose it programable? Can…

  • [FAQ] AM625/AM623 Custom board hardware design – Reading DEVICE_ID and Unique SOC (CPU) ID

    I have the below queries regarding the DEVICS_ID Is there a device ID available that I can read? Can you guide me how to read the device ID? Is the ID unique for each device? Is there an ID that is unique to each device?

  • [FAQ] AM625: Crystal drive strength specifications

    Part Number: AM625 Hello, Do we have a specification on the max drive strength/ power that AM625 can drive for both the HF crystal as well as 32 KHz oscillator? I didn't see it specified in the data sheet and customer wants to make sure they're within…

  • [FAQ] How to synchronize the PRU IEP timer with Linux system time?

    I am using a Sitara processor with a Linux core, a time sync router, and a PRU subsystem (AM62x, AM64x, AM65x). I want to synchronize the Linux system time with an IEP timer in the PRU subsystem. How do I do it? We will use AM64x for this example, but…

  • [FAQ] PROCESSOR-SDK-J7200: How to change/generate the “Eth” configuration for MCAL Ethernet Application from one core to other core.

    Part Number: PROCESSOR-SDK-J7200 Other Parts Discussed in Thread: DRA821 , DRA829 , SYSCONFIG How to change/generate the “Eth” configuration for MCAL Ethernet Application from one core to other core.

  • [FAQ] AM6412: AM64x SoC power supply slew control for 3.3V_SYS using load switch

    Part Number: AM6412 Other Parts Discussed in Thread: TPS65219 Hi team, I'm helping my customer design the power part of AM64. For the power supply slew rate control part, it says the slew rate should be controlled under 18mV/us. How should we set…

  • [FAQ] Redundant boot from eMMC boot partitions on AM62x

    1. booting from eMMC boot partition vs UDA partition It is recommended to use eMMC boot partition for user's BootLoader (BL) - eMMC boot partition is designed for bootloader user case - it is possible to write-protect boot0/boot1 as necessary - eMMC boot…

  • [FAQ] AM62A3: Any way to get 2 eMMC interfaces?

    Part Number: AM62A3 Hello, Using the AM62A, is there any way to implement two eMMC interfaces? The device has 3 MMC interfaces but the datasheet only shows MMC0 supporting eMMC. We really need a way to get 2 so I'll ask a couple questions from someone…

  • [FAQ] PROCESSOR-SDK-TDAX: How to change input display pipeline in the DSS M2M WB node?

    Part Number: PROCESSOR-SDK-TDAX The patches shared on below link adds support for DSS memory to memory path in the vision apps and TIOVX. These patches are also integrated SDK8.6. By default, this patch uses VIDL2 pipeline as input pipeline and WB pipeline…

View FAQ threads
  • Threads 197764 Discussions