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Frequent questions

  • [FAQ] AM620-Q1 / AM625-Q1 Custom board hardware design - Design and Review notes for Reuse of SK-AM62-LP Schematics

    Part Number: AM625-Q1 Other Parts Discussed in Thread: SK-AM62-LP , SK-AM62B-P1 , SK-AM62B , SYSCONFIG , AM625 Hi TI Experts, I am starting a new board design and planning to use TI Starter Kit (SK) design files for designing my custom board. https…

  • [FAQ] AM625 / AM623 / AM620-Q1 / AM62L / AM62Ax / AM62D-Q1 / AM62Px / AM64x / AM243x Design Recommendations / Commonly Observed Errors during Custom board hardware design – SOC peripherals and IOs connection when not used

    Part Number: AM625 Other Parts Discussed in Thread: AM62L Hi TI Experts, I am designing my custom board using TI AM62x family of processors. I have a few queries. 1. I am expecting to not use some of the SOC peripherals. Do you have a recommendation…

  • [FAQ] PROCESSOR-SDK-J721S2: Enable DP->HDMI adaptor on SDK9.x release

    Part Number: PROCESSOR-SDK-J721S2 This article provides the changes required to enable DP->HDMI adaptor on SDK9.x release.

  • [FAQ] AM623: MCU_OSC0_XI starts timing slot is not correct

    Part Number: AM623 Hi, TI Expert [Problem] : We found "MCU_OSC0_XI/MCU_OSC0_OUT" clock starts timing "forward" than VDD_CORE voltage pull high. (Customized board) Normal timing should be like this chart. MCU_OSC0_XI/MCU_OSC0_OUT starts after VDD_CORE…

  • [FAQ] AM6x: UART Boot and Download Speed Optimizations (25+% !!!)

    Part Number: AM625 Other Parts Discussed in Thread: SK-AM64B , SK-AM62B Overview The UART boot mode available on AM6x processors (and other similar TI devices) is a valuable tool often used during development and board bringup. To load the initial…

  • [FAQ] AM62A7: Is it possible to adjust the timing of RMII TXD? RMII connection with Ethernet Switch IC - MAC-MAC RMII loopback

    Part Number: AM62A7 Hello. I'm developing custom board which has RMII connection with Ethernet Switch IC. The AM62A and the Ethernet switch IC are connected via MAC-to-MAC mode. The message 'eth0 Link is up' appears, but the ping command fails. I…

  • [FAQ] TDA4VM: How to enable/use wake-up domain UART for collecting EthFw debug logs? when we not have Main Domain UART on Board.

    Part Number: TDA4VM How to enable/use wake-up domain UART for collecting EthFw debug logs? when we not have Main Domain UART on Board.

  • [FAQ] DP83869: Clock input Xi range AM644x AM64x use case

    Part Number: DP83869 Hi Ethernet Team , I have a question on the Xi clock input level. The DP83869 EPHY IO supply is 3.3V The Clock buffer supply is 1.8V. Based on the below, looks like this should not be a issue. Any thoughts please. Regards…

  • [FAQ] PROCESSOR-SDK-AM62A: How do I benchmark a neural network model on the Edge AI SDK for the AM62A or other AM6xA devices?

    Part Number: PROCESSOR-SDK-AM62A Other Parts Discussed in Thread: AM62A74 , AM68A , AM62A3 , AM69A I made a model and what to understand how fast it can run on an AI accelerated device like the AM62A. I see variations in performance based on which scripts…

  • [FAQ] TDA4VH-Q1: CDD_IPC_APP_RC_LINUX example for J784S4 is not present in SDK 9.1

    Part Number: TDA4VH-Q1 Hello, Can you please provide CDD_IPC_APP_RC_LINUX example for J784S4 in SDK 9.1 ?

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