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AFE7950: Signal generation from DAC AFE7950EVM

Part Number: AFE7950

Tool/software:

Dear TI Team,

I am currently working on a setup involving the AFE7950EVM, where I aim to generate a 1 GHz sine wave, send it to the DAC, and process the looped-back ADC data via the FPGA JESD interface. I have a few queries and would greatly appreciate your assistance in resolving them:

  1. DAC Sampling Rate:
    The DAC sampling rate displayed in the Latte GUI is mentioned as 2949.12 * 4 = 11,796.48 MSPS. Could you please explain why this multiplication by 4 is performed? and I can change or not how?

  2. Frequency Calculation for Custom Sine Wave (64-point LUT):
    I calculated the sine wave frequency as 184.32 MHz(clock) / 64(point) = 2.88 MHz based on the customized 64-point sine wave generated from the sine_64point.v Verilog code. Is this the correct frequency? If not, could you clarify the expected frequency? given 64 point Verilog code?

  3. NCO Frequency Configuration:
    In the Latte GUI, I modified the NCO frequency using the following configuration:

    sysParams.txNco0 = [[1000,1000], # Band0, Band1 for TxA for NCO0
    [1000,1000], # Band0, Band1 for TxB for NCO0
    [1000,1000], # Band0, Band1 for TxC for NCO0
    [1000,1000]] # Band0, Band1 for TxD for NCO0
  1. Are there additional configurations I need to ensure proper operation, or is this sufficient?

  2. SYSREF and Reference Clock:
    I have connected sysref_p and sysref_n from the AFE7950EVM to the FPGA. The system clock (sys_clock) is set to 184.32 MHz, as specified by the EVM.

    verilog code:
    wire sysref; IBUFDS sysref_ibuf (.I(sysref_p), .IB(sysref_n), .O(sysref)); assign rx_sysref = sysref; assign tx_sysref = sysref;

    Could you confirm the reference clock (ref clock) frequency from the AFE7950?

  3. JESD Data Rate and Sampling Rates:
    After processing through the JESD interface, what is the expected data rate? How is this data rate related to the ADC and DAC sampling rates?

  4. 1 GHz Sine Wave LUT:
    Could you provide a LUT or samples data for generating a 1 GHz sine wave using the AFE7950 DAC?

gui

verilog code

I have connected the DAC output to the ADC input via RF cable (J9 to J3) on the AFE7950EVM. I look forward to your guidance to ensure proper configuration and understanding of the data flow.

Thank you.

Best regards,
Banoth Balu

  • Dear TI Support Team,

    I am currently working with the AFE7950 DAC and have encountered some challenges related to the output signal when using a 12-point sine wave configuration.

    I have attached a detailed document outlining my setup, observations, and specific questions about the DAC operation and configuration.

    Attachment:

    • A document detailing the issue, the setup parameters, observations, and specific questions regarding the DAC configuration.

    Request: I kindly request your review of the attached document and guidance on resolving the issue. Any insights or recommendations would be greatly appreciated.

    I modified the NCO frequency to 1 GHz using the GUI and wrote a Python script to generate the 12-point sine wave.

    I wanted to confirm if this approach is correct for achieving a 1 GHz signal from the DAC ?.

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    '''
    Validation : AFE79xx Library Version
    v1.67, v1.74
    Case RX TX FB CLK Notes
    ---- ----------------- ----------------- ----------------- ----------- ------------
    1 245.76Msps, 24410 491.52Msps, 44210 491.52Msps, 22210 FADC=2949.12M DAC in interleaved mode
    SerDes=9830.4Mbps SerDes=9830.4Mbps SerDes=9830.4Mbps FDAC=8847.36M
    PLL0, NCO=3500M PLL0, NCO=3500M NCO=3500M REF=491.52M
    2 245.76Msps, 24410 491.52Msps, 44210 491.52Msps, 22210 FADC=2949.12M DAC in straight mode
    SerDes=9830.4Mbps SerDes=9830.4Mbps SerDes=9830.4Mbps FDAC=8847.36M
    PLL0, NCO=3500M PLL0, NCO=3500M NCO=3500M REF=491.52M
    '''
    setupParams.skipFpga = 1
    sysParams = AFE.systemParams
    setupParams.fpgaRefClk = 184.32
    AFE.systemStatus.loadTrims = 1
    sysParams.fbEnable = [False]*2
    sysParams.FRef = 491.52
    sysParams.FadcRx = 2949.12 #adc sampling Rate
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    AFE7950_DAC_Query.docx

    One more point: regarding lanes in gui 0 1 2 3 4 5 6 7

    In .vh hedder file in verilog given for dac 4,5,6,7,3,0,1,2 and adc 5,4,6,7,3,0,1,2

    Best regards,

    balu

  • Dear Ti Team,

    can anyone answer this?