[FAQ] AM6442, AM6441, AM6422, AM6421, AM6412, AM6411 and AM2434, AM2432, AM2431 (ALV, ALX) Custom board hardware design – Queries regarding Crystal selection and clock specifications

Hi Board designers, 

Refer below inputs for the queries related to the MCU_OSC0 crystal selection. 

10. MCU_OSC0_XI/MCU_OSC0_OUT starts before VDD_CORE voltage ramps up, is this a concern

The oscillator is working as expected. It most cases the oscillation will start shortly after its 1.8V power rail is applied, but there may be conditions where it doesn't start until after VDD_CORE is applied.

11. Does it have any side effect when MCU_OSC0_XI clock starts before VDD_CORE voltage ramps up? What kind of conditions let MCU_OSC0_XI doesn't start until after VDD_CORE is applied?

No side effects.

The oscillator has registers in the VDD_CORE power domain that controls some of its operating functions. It is very unlikely the start-up will be delayed until VDD_CORE is valid, but we are being conservative by saying the oscillation will not begin until VDD_CORE is valid to ensure the product designer provides adequate time for the oscillator to start before reset is released.

(+) [FAQ] AM6442: question about MCU_OSC0 Start-up - Processors forum - Processors - TI E2E support forums

[FAQ] AM6442: question about MCU_OSC0 Start-up

I have a question about "Figure 7-16. MCU_OSC0 Start-up Time" from the datasheet. Here it looks like that MCU_OSC0 is only allowed to start when VDD_MCU is ramping. In reality the osciallation starts already with VDDS_OSC0, while VDD_MCU is still disabled. 

I assume that this is OK and not causing any problems?! But if this is the case, why is the Start-up Time ts shown relatative to VDD_MCU stable? Shouldn't it be related to VDDS_OSC0 stable?

The oscillator is powered from VDDS_OSC0. So it may power-up and begin oscillation as soon as VDDS_OSC0 is applied. However, the oscillator has a few control registers which are powered by the VDD_CORE domain. So there is a chance the oscillator may not start until the VDD_CORE is valid. 

The supply shown in the upper waveform should be named VDD_CORE rather than VDD_MCU. AM64x does not even have a power rail named VDD_MCU. Therefore, I need to get this figure updated in the datasheet. Thanks for asking the question, which highlighted the error in the figure. 

12. It is assumed that when a crystal connected externally has a large change in frequency due to some factor, there will be an effect on the PLL.

I would like to know the effect on the PLL when the frequency changes and how each function will operate. The factors that may cause the frequency to change include initial failure, environment, and manufacturing defects.

Ans: It is not possible for crystals to have a large change in frequency. They have a very high-Q impedance response. The impedance drops dramatically with a very small shift in frequency, which would cause the gain in the oscillator feedback path to drop such that it is not possible to maintain oscillation. So, they are either oscillating at their designed frequency are not oscillating.

13. Does the 25MHz XTAL has an oscillation margin switching function and is there need to configure registers.

No HFOSC0 registers are required to be changed. These registers should remain in their default state.
Select the appropriate crystal circuit components that are compliant to the values defined in the MCU_OSC0 Crystal Circuit Requirements table.
Read the Load Capacitance and Shunt Capacitance sections to select the appropriate crystal circuit components.

14. Do you have some recommendations on the crystal load and load capacitance matching 

It is recommended to match the crystal load and the load capacitance as per the data sheet recommendations. Any difference in the crystal load and the load cap capacitance selected could result in PPM variation of the clock frequency Choose crystal load as per the standard capacitance availability to ensure matching of the capacitance.

References

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1115457/am6411-is-it-needed-to-input-the-synchronized-clock-between-am64x-and-ethernet-phy

Regards,

Sreenivasa

Hi Board designers, 

Additional references:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1292714/am3352-crystal-resonator-maximum-load-capacity/4907439#4907439

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/998892/am3352-crystal-osc0---parameters---esr-and-behaviors

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/331843/crystal-frequency-stability-and-tolerance-for-osc0-on-am3352

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/332473/osc0-crystal-the-max-start-up-time-on-am3352

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/921582/amic110-min-value-of-tsx-start-up-time-of-osc0-crystal-circuit

Regards,

Sreenivasa

Hi Board designers, 

Additional references:

MCU_OSC0 LVCMOS Digital Clock Source

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1381636/am6442-for-pin-c21-b20-we-use-lvcoms-digital-osc-how-should-i-connect-c21-and-b20-i-didn-t-found-the-specification-thanks/5279659

(+) AM6412: AM64x MCU_OSC0 LVCMOS Digital Clock Source specification - Processors forum - Processors - TI E2E support forums

(+) [FAQ] AM6442, AM6441, AM6422, AM6421, AM6412, AM6411 and AM2434, AM2432, AM2431 (ALV, ALX) Custom board hardware design – Queries regarding MCU_OSC0 LVCMOS Digital Clock Source - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa

Hi Board designers, 

Additional references for crystal selection

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1038770/am3358-frequency-tolerance-and-frequency-stability-of-24mhz-crystal/3841749

The accuracy of the AM335x reference clock source should be based on system level requirements. For example, you may need a 30 PPM reference clock if an AM335x timer is being used to operate something that needs this level of accuracy. 

The 50 PPM limit was defined for AM335x because the RMII Ethernet standard requires this accuracy. The other Ethernet standards only require 100 PPM, so you may be able to back-off on this 50 PPM requirement if not using RMII. However, this depends if you have other system function that require an accuracy of 50 PPM. I would not recommend going above 100 PPM as this may begin to effect other peripheral interfaces.

Keep in mind, a crystal has three contributions to accuracy. There is a parameter that defines initial accuracy, another parameter that defines accuracy over operating temperature, and aging parameter that defines how much the resonate frequency changes over time due to aging effects. When selecting a crystal, you must combine all of these to determine frequency accuracy across all operating conditions for the life of the product.

Reliable start-up is also a concern with crystal selection. The max ESR of the crystal is one of the primary concerns. The AM335x oscillator may not have enough gain to reliably start oscillation if the crystal ESR is too low. Many crystal datasheets define a worst case max ESR value for the entire family of crystals rather than a specific max ESR for the crystal being selected. In most cases the higher frequency crystals in the family will have a much lower max ESR value that what is found in the datasheet. Therefore, you may need to contact the crystal manufacture and request a device specific datasheet for the crystal part number you plan to use.

One way to confirm you have start-up margin, is by inserting a resistor in series with the selected crystal and checking for reliable start-up across all operating conditions. I suggest you begin with a resistor value that is about 5x the max ESR of the crystal. If you have start-up issues with this value you can reduce it to 3x. There is not enough gain margin if oscillation will not reliably start with a 3x resistor. You would need to select a crystal with lower ESR if you find it will not reliably start with a 3X series resistor.

You neve said if you were using RMII and needed 50 PPM system performance. Therefore, I cannot comment how were these options align with your system requirements.

I noticed the Digi-key description for your existing crystal, which they are selling under part number 7A-24.000MAAJ-T was cut for an 18pF load, so it must not be one of the standard options shown in the datasheet. What load did you apply to this crystal in your product? Are you willing to change load capacitor values in your product when you change crystals? How much capacitive load does you signals apply to the crystal circuit?

I do not think a crystal cut for 18pF load was ever appropriate for AM335x. Each load capacitor would need to be approximately 33 - 36 pF to achieve a 18pF load for the crystal and the AM335x datasheet only allows load capacitors in the range of 12 - 24 pF. 

The highest load capacitance crystal you would be able to use is 12pF to remain in the ranged defined by the AM335x datasheet.

The AA-24.000MAHJ-T datasheet shows their standard offering is a crystal cut for a 8pF load. However, they provide an option to specify a load capacitance. I did not see an aging parameter in this datasheet, so not sure how PPM will change over time on this crystal.  It may be a viable option as long as you apply the correct load capacitance for the crystal your purchase while remaining compliant with AM335x datasheet. However, you should validate startup reliability using the method described previously to ensure ESR in not going to be a problem.

The ECS-240-18-30-JGN-TR datasheet does not clearly show an option for buying a crystal cut for a lower capacitive load and 20 pF is too high. You may be able to use this as a viable option if they would sell you one that was cut for 10 pF.

AM3352: Crystal OSC0 - Parameters - ESR and Behaviors

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/998892/am3352-crystal-osc0---parameters---esr-and-behaviors/3690471

The biggest concern is not having enough gain margin to reliably start oscillation when the higher ESR crystal is combined with the other crystal circuit components and internal oscillator.

There is a good chance you have enough gain margin if this combination of components has been used for a while without receiving any reports of the oscillator not starting.

In most cases the actual ESR of a crystal is much smaller than the published value. This is especially true when the ESR value you are using is taken from a data sheet that covers an entire family of crystals. The max ESR value published in a crystal family data sheet is typically inflated to cover the entire range of crystals. You may be able to reach out to the crystal manufacture and request a part number specific datasheet to confirm the max ESR of your crystal.

You can test the gain margin by placing a resistor in series with the crystal, which increases the ESR seen my the entire circuit. We typically recommend confirming reliable start of oscillation across operating conditions when the series resistor inserted increases the ESR to at least 3x the expected ESR of the crystal. 

Load capacitor values should be selected based on the load expected by the crystal. Crystal are cut to oscillate at the specified frequency with a specific capacitive load. The frequency of oscillation will be pulled a few PPM from the specified frequency if the load you apply is not correct. Most crystal manufactures provide a service where they evaluate your product with their crystal and make recommendations if your initial component selection is not optimum. I think the fee they charge is reasonable for any high volume product where you want to be confident that you clock solution is robust.

Regards,

Sreenivasa

Hi Board designers, 

Refer below FAQ for information related to Oscillator specifications being added to all the processor family data sheets and use of BAQ oscillator:

(+) CDC6C: BAW oscillator use for AM6442 - Clock & timing forum - Clock & timing - TI E2E support forums

LMK6CE02500DDLFT

e2e.ti.com/.../am6442-can-i-use-this-oscillator

Regards,

Sreenivasa

Hi Board designers, 

AM62A3-Q1: HW : crystal failure

It is assumed that when a crystal connected externally has a large change in frequency due to some factor, there will be an effect on the PLL.

I would like to know the effect on the PLL when the frequency changes and how each function will operate.

The factors that may cause the frequency to change include initial failure, environment, and manufacturing defects.

It is not possible for crystals to have a large change in frequency. They have a very high-Q impedance response. The impedance drops dramatically with a very small shift in frequency, which would cause the gain in the oscillator feedback path to drop such that it is not possible to maintain oscillation. So, they are either oscillating at their designed frequency are not oscillating.

Regards,

Sreenivasa

Hi Board designers, 

Information related to clock source (oscillator) placed on carrier board:

Q. The oscillator is placed on the carrier board and the clock is connected through a connector to the processor.
My question was on the clock length and related concerns.
Checking if there are any concern or care-abouts for customer to take care while placing the oscillator on the carrier board or should customer place the oscillator on the processor board and is there a recommendation or requirement to place oscillator close to processor like the crystal.

A.

The digital output of the LVCMOS clock source with fast rise/fall times will be more tolerant to noise than the near sinusoid signal that is produced by the crystal circuit, so placing it near the processor is not as important as the crystal circuit. They need to follow the recommendations in the following notes and confirm the Rise/Fall Time (10%-90% rise, 90%-10% fall) is less than 4ns at the MCU_OSC0_XI pin.
Note
1. A DC steady-state condition is not allowed on MCU_OSC0_XI when the oscillator is powered up. This is not allowed because MCU_OSC0_XI is internally AC coupled to a comparator that can enter an unknown state when DC is applied to the input. Therefore, application software must power down MCU_OSC0 any time MCU_OSC0_XI is not toggling between logic states. 2. The LVCMOS clock signal sourcing the MCU_OSC0_XI input must have monotonic transitions.
The clock source should be connected to MCU_OSC0_XI with a point-to-point connection, via a series termination resistor placed near the clock source. The series termination resistor value should match the clock source output impedance to the transmission line impedance. For example, the series termination resistor value needs to be 20 ohms if the clock source has an output impedance of 30 ohms and the PCB signal trace has a characteristic impedance of 50 ohms. This allows the reflection that returns from the far end of the un-terminated transmission line to be completely absorbed such that is does not introduce any non-monotonic events on the signal.
3. The PCB trace length connecting the LVCMOS clock source to MCU_OSC0_XI should be minimized. This reduces capacitive loading and decreases probability of external noise sources coupling into the clock signal. Reduced capacitive loading improves rise/fall times of the clock signal which reduces the probability of jitter being introduced in the system.

My biggest concern is related to ground noise introduced by the two PCB implementation. Any ground noise (high frequency potential difference between the grounds of each PCB) will appears as noise on any signal that is sourced from a device on the carrier PCB to our device on the processor PCB. They need to have a lot of ground pins on the connectors that connect the two PCBs. I would say at least one ground for every two or three signals that transition from one board to the other.

Regards,

Sreenivasa

Hi Board designers, 

Queries related to SOC start-up with crystal not operating

Will it switch to CLK_12M_RC even if HFOSC0 is not oscillating at cold start?
[TI] >> By default MCU_PLL_CLKSEL_CLKLOSS_SWTCH_EN is set to ‘0’. So at cold start, if HFOSC0 is not switching then the mux will not switch to CLK_12M_RC. If HFOSC0 is not switching during cold start, the device will not boot-up.

Did you have a chance to power cycle the board and see the behavior with the oscillator disabled.

5.4.4 Device Oscillators
The device has the possibility to source clocks of an external high-frequency oscillator - MCU_HFOSC0. The
device has also one internal RC oscillator - MCU_RC_OSC_12M.

Oscillator Clock Loss Detection

Observation clocks

One more observation we had capture, we monitored the OBSCLK0 output using an oscilloscope. We mapped the OBSCLK0 pin to output MCU_HFOSC0_CLKOUT:

• When the 25 MHz external clock is active, we observe 25 MHz on the oscilloscope.
• After the fallback, the output changes to 12.5 MHz.
• However, when the external 25 MHz clock is re-enabled, the oscilloscope again shows 25 MHz, but the processor continues to run on the internal 12.5 MHz clock.

Regards,

Sreenivasa

Hi Board designers, 

Inputs related to IBIS model for Xi

NC is the expected connection for the AM64x, AM62x, AM62Ax, AM62Px and AM62L family of processors. This is the crystal or oscillator input. We do not provide any IBIS models for the clocking section IP of the processor.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/752136/tms320c6746-ibis-model-for-l19-oscin-pin/2782761

I checked a couple of other IBIS files available on TI.com, and they also do not provide model data for the oscillator inputs (even if used as an clock input from some LVCMOS oscillator source instead of a crystal).

I suspect the reason is because these clock/crystal inputs are analog in nature, but I will follow up with our IBIS expert. IBIS files are meant for IO buffers.

This NC for OSCIN/CLKIN pins is consistent with other devices.

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/274626/f2812-pgf-ibis-model-clk-is-nc-signals

We checked with our Design team on this and got the following reply:

"We do not provide IBIS models for power/ground/Oscillator pins.  Usually SI simulations are significant for drivers.  X1 being a receiver may be modeled as a simple cap".  

Just to clarify further, SI simulations are significant primarily for drivers. i.e. Signal integrity simulations are useful only for I/O pins and not for input-only, clocking pins like X1.  

OMAP-L138: OSCIN (pin L19) missing in IBIS model?

OSCIN input (pin L19) is missing in OMAP-L138 IBIS model. Do we have updated IBIS file?
 
Or is OSCIN not required for IBIS? Having said this should customer try to find an option on his compilation tools to ignore these pins…

Generally speaking, OSC inputs are not simulated, especially if an actual crystal is used.  IBIS does not simulate analog inputs.

Regards,

Sreenivasa