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OPA365-Q1: Ringing on op-amp output

Part Number: OPA365-Q1
Other Parts Discussed in Thread: OPA365, INA240

Good day Ti,

I build a new motor controller board with low side current sensing and the OPA365 as op-amps. On the op-amp output there are heavy oscillations. All other waveforms like the phase or the gate voltages looks very good, there is almost no ringing.

 

I think I know where they come from but I’m not sure, if there is something I can do against it and wanted to ask you if you have any ideas or comments to this.

Because of the inductance of the shunt resistor and the supply path I added a 1uf capacitor between drain of the high-side fet and source of the low-side fet to suppress the initial voltage pulse on the source of the low-side fet.

This capacitor reduces the initial voltage pulse, but I think it is forming an LC-Circuit with the inductance of the shunt and supply path and this causes the oscillations. Do you also think that is the cause or is there something that I didn't think of?

Here is a picture what I mean:

But when I remove the Capacitor (in the picture above, the yellow C) between HS-FET drain and LS-FET source, the ringing reduces a lot, in simulation and on the real board. On the other side, when I remove this capacitor I have a larger voltage spike on the source of the LS-FET, which could be damage the DRV. Should I consider using a lower capacitance? At the moment it is 1uF.

Here are two pictures of the opamp output when measuring the current, it’s only about 4A in this picutures:

This is with HS-Drain – LS-Source capacitor:

This is without HS-Drain – LS-Source capacitor:

And here are two pictures from the voltage between ground and LS-Source:

This is with HS-Drain – LS-Source capacitor:

This is without HS-Drain – LS-Source capacitor:

Most of the time I used inline sensing with an INA240 for example where I don’t have this problem. It would be nice to know if there are some things that help would help in this case. I can’t change the inductance of the shunt, I already uses shunts with low inductance, and I think the layout should be ok, there are some pictures at the bottom and all schematics.

What I’ve done so far, I changed the input filter of the op-amp and the oscillations reduced many.

In the picture below you can see the circuit before I change the filter. The values in the picture are the real values.

Here is the output of the op-amp on the board: (It looks much worse if C69 and C68 are not placed)

With the values below, the ringing reduced a lot with this:

As you can see here:

But this reduces the cutoff frequency to about 400kHz, I won’t go lower. How do I determine the minimum bandwidth for an op-amp used in low side current sensing (for inline it’s clear for me). The OPA365 has definitely enough bandwidth. I saw a lot of rule of thumb formulas but on what does it really depend? Do you have an app note for this?

My sampling time of all three phases is about 150ns-500ns depends on the MCU. PWM frequencies are between, 10kHz and 40kHz. Minimum on time of the low side fet of duty is 2-3us min and usually 5us. Sampling happens in the middle of the on time from the LS-FET at which point the voltage should already have settled to a reasonable value.

di/dt is about 80A in 30ns-40ns on the shunt resistor. 80A is the maximum current to measure, there I have about 80mV on inputs of the op-amp (1mOhm shunt, gain is 20). This is a dv/dt of  2V/us.

 

What I didn’t try so far what this kind of filter, maybe there is less ringing, but the settling time would be the quite same I think.

Here are the layout and schematics:

op-amp circuit:

op-amp layout:

routing of the sense traces:

Best regards and thank you in advance,
Daniel

  • Hey Daniel, lot of good information here, but what is the load on the op amp output? 

  • Hello Michael,

    yes, I forgot to add it. The load on the op-amp output is the ADC of the F28069m, here is a picture of the adc:

     

    Before the ADC is a charge bucket filter 50Ohm, 33pF:

    Here is the layout:



    Best regards,
    Daniel

  • Hello Daniel,

    Thank you for the update and the great information shared; I will also take a look and get back with questions.

    Oscillations can be an adventure to track down; I'll make sure to ask my broader team about this as well.

    Best,

    Alec

  • Hello Alec, you're welcome, I say thank you for your help, if you need anything else just let me know. I'm excited to see what comes out.

    Best regard,
    Daniel

  • Hello Daniel,

    Great; I will work on getting back to you next week.  Today and Friday are quite busy already.

    Best,

    Alec

  • Hey Alec,

    just some updates.  Because of the oscillations, I will try to add a series resistor to the capacitor to damp the oscillations, maybe this could help, I will do some tests and update the results here on Friday.

    Best regards,
    Daniel

  • Hello Daniel,

    Thank you for updating me.  I will look out for any updates.

    Best,

    Alec

  • Hello Alec,

    first sorry for the long delay. Something went wrong with my component order in my work. A few resitors for the testing arrived yesterday. I did a quick test with an 30mOhm resistor in series with capacitor. I've noticed an improvement, but I need more time and the other resistances to investigate further.

    I will report then.

    Best regards,
    Daniel

  • Hello Daniel,

    Thank you for the update.

    Best,

    Alec

  • Hello Alec,

    I finished the testing. I used this resitor values for testing: 0, 10m, 20m, 50m, 100m, 200m, infinity (no resistor) with 1A, 5A, 20A. As expected, the lower the resistance the higher the transients.

    I will use 200m because the capacitor definitely influences the current measuring and that’s important for me also the negative and positive voltage spikes on the source of the Mosfets are in a reasonable range and I expect no problems with this, lets see :) At 60Amps (maximum) I will have about 3V negative spike with the 200m resistor, which is not so bad.

    The values for the input filter I will use are 20 Ohm with 6.8nF, picture below. Cut-off at about 600kHz, which should be fine for my application.

     

    Here are a few plots.

    1a. These are the measurements without input filter at 5A:

    1b. Here is the same with 20A:

    1c. Here are 5A with different input filter:

    1d. And the final measurement with 200m resistor and 6.8nF input filter capacitor:

    What’s interesting, if you look at picture 1a or 1b, phase b has inherently more oscillations compared to phase-a or phase-c. Although phase-b has a higher resistor in series compared to phase-a, phase-a looks better. Don’t know why, same layout, same components. I will live with that.

    Thank you,
    Best regards,
    Daniel

  • Hi Daniel,

    the ringing can come from a lot of sources.

    I would try to increase the ESR of C33 by adding a small resistance of 0.10...1R in series to this cap. A resistor in 0805-package could do.

    Then, you should be careful when paralleling caps. This can result in huge resonances (->anti-resonance), especially when the paralleled caps both show ultra low ESR. You can again mount a small 0.10...1R 0805 resistor in series to at least one of the two caps being paralleled.

    But also electrolytic caps can make issues when connecting a too small capacitance in parallel. If the paralleled cap is a ceramic cap, increase the capacitance from 10...100n to 470n...10µ. In certain cases adding a small 0.10...1R 0805 resistor in series to the ceramic cap can again help.

    Another cause of ringing can be common mode noise between the grounds of shunt and OPAmp circuit. The best way to minimize it, is to use a solid ground plane and to move the OPAmp close to the shunt. Feeding the signals from the shunt to the OPAmp inputs through a common mode ferrite choke can also help. If you form a common mode filter with this common mode ferrite choke, adding series resistors can help to dampen resonances.

    Another trick is to minimize the ringing in the FET-stage itself by threading one or more terminals of FETs through a small ferrite bead. Of course, this must be checked out very carefully.

    Kai

  • Hello Kai,

    first of all, thank you for writing me :)

     

    Kai:
    I would try to increase the ESR of C33 by adding a small resistance of 0.10...1R in series to this cap. A resistor in 0805-package could do.

    In my post above I tried exactly this. Before I put this resistor in my layout, I had read that this can maybe affect the current sensing. I think this was not maybe in my case.  

    So, I tested resistors from 10mOhm to 200mOhm in series to C33. I will use the 200mOhm, the results are much better now. Also added a filter with 6.8nF and 20Ohm, the circuit is in the post above.

    Kai:
    Then, you should be careful when paralleling caps. This can result in huge resonances (->anti-resonance), especially when the paralleled caps both show ultra low ESR. You can again mount a small 0.10...1R 0805 resistor in series to at least one of the two caps being paralleled.

    Thank you for the tip. I do not have really have nF caps in parallel, except a lot 100nF bypass caps on the 3.3V rail. The 3.3V are very clean, I think this shouldn’t be a problem then?

    I have a few 2.2uF in parallel for the decoupling of the inverter stage, but you mentioned in the microfarad range it’s not so bad.

    The more the voltage will change on the parallel capacitors, the more this oscillation will be, right?

    Can you tell me a real circuit/application where this can cause problems?

     

    Kai:
    Another cause of ringing can be common mode noise between the grounds of shunt and OPAmp circuit. The best way to minimize it, is to use a solid ground plane and to move the OPAmp close to the shunt.

    I did my best with the layout (picture below), split the ground once but just because there are about 60 amps on the power stage. On the logical part, I have two solid ground planes on layer 2 and layer 4.

    I understand to keep the traces very short from the shunt to the opamp if I do high-side sensing. Is it also important for low-side sensing?

     

    Kai:
    Feeding the signals from the shunt to the OPAmp inputs through a common mode ferrite choke can also help. If you form a common mode filter with this common mode ferrite choke, adding series resistors can help to dampen resonances.


    Do you know some books or application notes which you can recommend, for the things you mentioned above. I know what a common mode choke is, but not really how to use it.

     

    Kai:
    Another trick is to minimize the ringing in the FET-stage itself by threading one or more terminals of FETs through a small ferrite bead. Of course, this must be checked out very carefully.

    I’ve never heard of that, do you mean in series to drain or source? I’ve seen it for the gate.

     

    Best regards,
    Daniel

  • Hello Daniel,

    I am waiting on an update from a team member regarding if we have any relevant app notes to assist you.

    Best,

    Alec

  • Hello Alec,

    thank you, thats very nice!

    Best,
    Daniel

  • Hi Daniel,

    Can you tell me a real circuit/application where this can cause problems?

    Here are some links:

    https://e2e.ti.com/support/amplifiers-group/amplifiers/f/amplifiers-forum/1018068/opa3690-video-buffer

    https://www.signalintegrityjournal.com/articles/1589-the-myth-of-three-capacitor-values

    https://electronics.stackexchange.com/questions/320363/antiresonance-of-multiple-parallel-decoupling-capacitors-use-same-value-or-mult

    experiments_with_decoupling_capacitors.pdf

    1030.c39e.pdf

    I understand to keep the traces very short from the shunt to the opamp if I do high-side sensing. Is it also important for low-side sensing?

    The common mode noise would still be present. The problem is the gap in the solid ground plane and that you traverse the gap with unfiltered signals. You inject so much noise from the lower ground plane into the upper ground plane that a split of ground plane doesn't make much sense.

    I would check out whether using a solid ground plane gives better results than a split of ground plane. You could link the two ground planes together by lots of wires for a test.

    Another remedy is to traverse the gap with ferrite beads instead of copper tracks. You could also try to put some ferrite material right on the copper tracks traversing the gap, directly on the printed circuit board.

    I’ve never heard of that, do you mean in series to drain or source? I’ve seen it for the gate.

    Yes, that's the usual way. But ferrite beads can also be mounted in the terminals of decoupling caps, diodes (recovery time issues) and TVS. Ferrite beads do three things, at low frequencies they add inductance and can by this lower resonance frequencies, at high frequencies they add ohmic resistances and can dampen resonances by adding ohmic losses. And they behave differently for small and large currents by going into magnetic saturation at higher currents. By this you can dampen the antiresonance between a TVS and a parallel cap, for instance, but at the same time allow the TVS to fully work at high currents (ESD, Surge and Burst).

    Unfortunately, ferrite beads are highly unlinear and you must check the benefit more by trial and error rather than by simulation or calculation.

    Kai 

  • Hi Daniel again,

    to make the circuit work with a continuous and solid ground plane (instead of using a gap), you may want use a printed circuit board with 70µm copper planes and/or a printed circuit board with more ground layers. Another option is to use a printed circuit board with a thick metal core normally serving as cooling layer. Or you could solder pieces of thick copper band directly on the board (vertically mounted !) shunting the 80A away from the ground plane.

    Kai

  • Hello Kai,

    thank you a lot for the links!!

    I think I should tell you my board specs:

    Logic part: L1(TOP) = POW,SIG ; L2 = GND ; L3 = POW/SIG ; L4(BOT) = GND
    I choosed this stackup because I have almost no components on the bottom layer, otherwise I would switch Layer 3 and Layer 4.

    Power part: L1(TOP) = GND ; L2 = Gate traces ; L3 = Sense traces from shunt to opa ; L4 = VDD

    All layer are 2oz copper.

    Kai:
    The common mode noise would still be present. The problem is the gap in the solid ground plane and that you traverse the gap with unfiltered signals. You inject so much noise from the lower ground plane into the upper ground plane that a split of ground plane doesn't make much sense.

    I would check out whether using a solid ground plane gives better results than a split of ground plane. You could link the two ground planes together by lots of wires for a test.

    Another remedy is to traverse the gap with ferrite beads instead of copper tracks. You could also try to put some ferrite material right on the copper tracks traversing the gap, directly on the printed circuit board.

     

    I thought a lot of times of splitting the logic and power part or not, I asked a lot of people, colleges and so on. On the beginning I didn’t want to split it, but they said I should do, because of the voltage drop on the power ground when the Mosfets are switching, so this cannot affect the logic ground.

    I’m really not a fan of splitting ground, but in this case, I thought maybe they are right. I know it’s absolute bad to route traces over a gap, but because the sense traces for the opamp are differential, I thought that would not cause any problems. The input impedance of the opamp’s is high and I only have a Cdiff filter on the opamp input, Cdm is very low, 100p.

    But what you said, sounds very interesting. I don’t really understand why this can happen although I have differential pairs, could you please explain that a bit, I’m very interested in this:

    You inject so much noise from the lower ground plane into the upper ground plane that a split of ground plane doesn't make much sense.

    I will use a lot of wires to connect the grounds together, I will test this!! I will also try it with ferrite beads instead of copper wires and ferrites in series with the traces that crosses the gap. All of that separately of course. What is with small capacitors to connect the grounds over the gap, would this also be worth to try?

    Would it be an idea to place the filter of the opamps on the power ground and then cross over the gap, with the filtered signals? But my cut-off frequency is not so low, about 600kHz.

    Low side sensing has advantages but also causes a lot of problems.

     

    Kai:
    Yes, that's the usual way. But ferrite beads can also be mounted in the terminals of decoupling caps, diodes (recovery time issues) and TVS. Ferrite beads do three things, at low frequencies they add inductance and can by this lower resonance frequencies, at high frequencies they add ohmic resistances and can dampen resonances by adding ohmic losses. And they behave differently for small and large currents by going into magnetic saturation at higher currents. By this you can dampen the antiresonance between a TVS and a parallel cap, for instance, but at the same time allow the TVS to fully work at high currents (ESD, Surge and Burst).

    Unfortunately, ferrite beads are highly unlinear and you must check the benefit more by trial and error rather than by simulation or calculation.

    Thank you for this information, I know what ferrite beads do but never thought to use it for TVS or parallel cap. Very intressting. It's been a while, I had some oscillations on a signal, in the simulation ferrites worked perfectly but when I tried it in reality, there was no difference. But maybe I used the wrong ferrites.

     

     

    Kai:
    to make the circuit work with a continuous and solid ground plane (instead of using a gap), you may want use a printed circuit board with 70µm copper planes and/or a printed circuit board with more ground layers. Another option is to use a printed circuit board with a thick metal core normally serving as cooling layer. Or you could solder pieces of thick copper band directly on the board (vertically mounted !) shunting the 80A away from the ground plane.

    I wrote my board specs on the beginning of this post. I’m using already 70um copper(2oz) and on the logic part I have two grounds, the power ground has only one. I know the layout is not perfect, the next time I will use copper stripes for the high currents.

    What do you mean with vertically mounted? Something like this? (My first board :) )

     

     

    This will be my next board, with an alu core:




    Kai, again thank you a lot for your time!!

    Best,
    Daniel

  • Hi Daniel,

    What do you mean with vertically mounted? Something like this? (My first board :) )

    Yes, very similar. By "vertically mounting" of bus bar I meant something like this:

    http://ezcircuits.net/zbxe/Lab/21991?ckattempt=1

    Of course, the soldering joints can add resistance again. So, either put several bus bars in parallel or use an rectangle profile bus bar with screws.

    Or a construction like this:

    http://wiki.lofarolabs.com/index.php/Building_the_Motor_Controller

    https://www.researchgate.net/figure/Phase-leg-with-the-PCBs-of-the-gate-drivers-during-the-assembly-process_fig1_239936158

    The concept of using a solid ground plane profits of the proximity effect: HF ground return currents concentrate in the ground plane directly under the signal track and spread the less the higher the frequency is. Of course, to allow this to work, the chips, transistors and passive components must provide connections sitting very close to the printed circuit board. So, a µC in a DIL40 package does not profit from the proximity effect very much, since most of the signal traces are within the DIL40 package and these are way too far away from printed circuit board. But a µC in a QFN package, e.g., does profit.

    In an application like yours the signal contains lower fequency components below let's say 10...100kHz and higher frequency components. The lower frequency components which would widely spread over the pronted circuit, would profit from the heavy bus bars providing a much lower DC impedance than the ground plane. So, the lower frequency components would concentrate in the bus bars of the power section and not spread all too much over the entire printed circuit board.

    And the higher frequency components would profit from the proximity effect and would also be concentrated in the power section, namely in the portion of ground plane of the power section.

    So, even without splitting the ground plane, by simply using massive copper in the power section and a solid ground plane for the whole circuit, the analog area of µC section can be made almost free of the heavy power currents.

    But if you split the ground plane and have no massive copper in the power section, you may generate lots of common noise and both edges of the gap in the ground plane may show heavy potential differencies at DC, AC and HF. And when you traverse the gap too low ohmically you may inject EMI from the power section directly into the analog section. Because of this you always have to use a higher impedance, at least at HF, when you move from one section to any other (analog to digital, or power to analog, or power to digital,. a.s.o.). This is also true when you have no splitted but a solid ground plane.

    I would recommend such a circuit for traversing the gap or moving from section to section:

    daniel_hm601_1.TSC

    This is only an example and shall demonstrate how to traverse the gap by the help of a ferrite bead. In this example the "FBMH1608HM601" is shown which I use very often in my circuits. Of course, also a common mode choke can be used and may even be a better idea. The ferrite bead must be located exactly over the gap. R3, R4 can also be located over the gap, but C1 and C2 have to be located in the analog section, of course. "VG1" represents the common mode noise between the two sections.

    With this technique you do both, traverse the gap by a high impedance, preventing EMI from being injected from one section to the other and you have a filtering, suppressing common mode noise. If the issue in your application actually is common mode noise then this technique will help.

    Kai 

  • Hello Kai,

    thank you for your great answers! It’s worth a lot to me!!

    I added something like a bus bar, but not sure if I need it, I tried to combine it with a “standard design”. It was more experimental, for my next boards, I will try to optimize this:


    Kai:
    The concept of using a solid ground plane profits of the proximity effect: HF ground return currents concentrate in the ground plane directly under the signal track and spread the less the higher the frequency is. Of course, to allow this to work, the chips, transistors and passive components must provide connections sitting very close to the printed circuit board. So, a µC in a DIL40 package does not profit from the proximity effect very much, since most of the signal traces are within the DIL40 package and these are way too far away from printed circuit board. But a µC in a QFN package, e.g., does profit.

    I tried to take care of this for all signals, except the signals that crossing the gap. As I mentioned I “hoped” that this would not cause any problems, but hope is not a good thing for engineering.

    Kai:
    In an application like yours the signal contains lower fequency components below let's say 10...100kHz and higher frequency components. The lower frequency components which would widely spread over the pronted circuit, would profit from the heavy bus bars providing a much lower DC impedance than the ground plane. So, the lower frequency components would concentrate in the bus bars of the power section and not spread all too much over the entire printed circuit board.

    That really makes sense!! I will overthink my motor control pcb designs.

     

    Kai:
    And the higher frequency components would profit from the proximity effect and would also be concentrated in the power section, namely in the portion of ground plane of the power section.

    Ok, but to take profit of the proximity effect in the power section, it should be also important that VDD and GND overlaps as much as possible and should be near together, right?

    Kai:
    So, even without splitting the ground plane, by simply using massive copper in the power section and a solid ground plane for the whole circuit, the analog area of µC section can be made almost free of the heavy power currents.

    Again, really makes sense, thank you, I’m looking forward to trying this with newer designs.

     

    Kai:
    But if you split the ground plane and have no massive copper in the power section, you may generate lots of common noise and both edges of the gap in the ground plane may show heavy potential differencies at DC, AC and HF. And when you traverse the gap too low ohmically you may inject EMI from the power section directly into the analog section. Because of this you always have to use a higher impedance, at least at HF, when you move from one section to any other (analog to digital, or power to analog, or power to digital,. a.s.o.). This is also true when you have no splitted but a solid ground plane.

    Never thought on that! If it does not make a lot of circumstances for you, would you know some example/reference circuits/links how to add higher impedance when changing sections? Just add resistors, ferrites, or chokes?



    Kai:
    This is only an example and shall demonstrate how to traverse the gap by the help of a ferrite bead. In this example the "FBMH1608HM601" is shown which I use very often in my circuits. Of course, also a common mode choke can be used and may even be a better idea. The ferrite bead must be located exactly over the gap. R3, R4 can also be located over the gap, but C1 and C2 have to be located in the analog section, of course. "VG1" represents the common mode noise between the two sections.

    With this technique you do both, traverse the gap by a high impedance, preventing EMI from being injected from one section to the other and you have a filtering, suppressing common mode noise. If the issue in your application actually is common mode noise then this technique will help.

     

    Thank you for the circuit. I have 0ohm resistors directly over the gap, I try ferrites instead! I will report the results, but it will take some time.

    Best,
    Daniel

  • Hello Daniel,

    Thank you for your update on action items, next steps, and follow-up questions.  TI also has resources for PCB Layout and High Speed Design, but the documents are admittedly difficult to find.

    If you do find a document or prior e2e thread on high speed layout & design, you may reconnect with me to ask any follow-up questions.

    Best,

    Alec

  • Hello Kai,

    I just tried your circuit because it took not long time.

    Instead of the ferrites you mentioned I only had these at home “BLM15AG601SN1D” and instead of the 100Ohm I used 75Ohm.

    I ordered the parts you mentioned (also some chokes) but they will come in 3-4 days.

    Will report then the results.


    Here is the same measurement only with your circuit (but the values used mentioned above):


    What do you say? I can not see a lot of difference on the first glance (same phase used, current and voltage). The spikes are higher but settles as fast as my old circuit.


    Here is it’s with the old values:

    Best regards,
    Daniel



  • Hello Alec,

    I have to say thank you because you are supporting me :)

    I will look for it, I have a few but they do not include the information I need.


    Best regards,
    Daniel

  • Hi Daniel,

    as I said, the shown circuit is only an example, not a ready solution. I would experiment with the component values of the low pass filter. And I would try a common mode ferrite choke as well. If the common mode ferrite choke does not help, then the peak is not caused by common mode noise but differential noise or, by other words, the peak is part of your wanted signal.

    You can treat and handle common mode noise and differential noise separately: Separate ferrite beads as shown in my circuit and a differential cap (your C93) suppresses differential noise and a common mode ferrite choke and common mode capacitances (your C34 and C35) suppresses common mode noise. By this you can find out what sort of noise the peak is.

    Since your signals are only in the 10kHz range, it may also be possible that the inductance of the shown ferrite bead is too small and that you may need to take an UKW choke offering a much higher inductance, like this one for instance, :

    https://www.reichelt.de/de/en/broadband-choke-0-75-kohm-06h-75-p1103.html?trstct=pol_3&nbc=1&&r=1

    These are also available as common mode chokes and they are fabricated in SMD as well.

    Again, my circuit only shows the idea of using ferrite beads to cross the gap, not a ready solution Relaxed

    Kai

  • Hello Kai,

    sorry for my late reply, I had a lot to do. First thank you for you answer.
    I thought this was not a ready solution, it is a starting point for me. I ordered a few smd ferrite chokes, they should come next week.

    In the meantime, I had an idea, I assume about 2-3nH on the shunt resistor. With u = L*di/dt, I got very reasonable values for the voltage spikes. I put two Schottky diodes antiparallel across the shunt, with a very low vfw. Maybe it’s not the usual way but it works not bad, especially with higher currents, what is good. I also considered the temperature curve of the diodes, I tried it with room temperature and I heated up the diodes to about 80°.

    Kai:
    “You can treat and handle common mode noise and differential noise separately: Separate ferrite beads as shown in my circuit and a differential cap (your C93) suppresses differential noise and a common mode ferrite choke and common mode capacitances (your C34 and C35) suppresses common mode noise. By this you can find out what sort of noise the peak is”

    That’s a great idea, very good tip, thank you!!!

    I will do some final measurements when I get the chokes and let you know, maybe it helps another one.

     As I saw your link from Reichelt I had to look on your profile. Then I saw you are from Germany, I’m from Austria, Salzburg Blush

     

    Best regards,
    Dani

  • Hello Kai,

     

    I mounted a ferrite choke before the op-amp input.

    This is the one I tried (Z=680 @100Mhz):
    https://www.mouser.at/ProductDetail/Laird-Performance-Materials/CMA0805A681R-1A?qs=By6Nw2ByBD0t%252BduWHcwEWw%3D%3D

    I also ordered a other one with a higher impedance hope it will come next week. (Z=9.5k @100Mhz)
    https://www.mouser.at/ProductDetail/TDK/ACT1210L-201-2P-TL00?qs=Mv7BduZupUihm29FxkL%2FmQ%3D%3D

    No differential filters are used on this picture only the ferrite choke and after a slight common mode filter on the op-amp input. Again with 20A.

    I think there is not much difference with only ferrites beads used instead of the choke:


    The peak of the spike does not change. I will try the other choke, maybe something will change then.

    But up to now, I think the spike is unfortunately my wanted signal, do you think the same?

    Best,
    Daniel

  • Hello Daniel,

    Thank you for the updates.  While I am on travel, my team will be monitoring this thread.

    Best,

    Alec