Part Number: LMK04828
Other Parts Discussed in Thread: DAC38J84
Tool/software:
I am trying to achieve a continuous SYSREF signal for debugging my JESD204B links.
The PLL1 isn't locked at the moment, but the PLL2 is sourced from a stable signal generator at 120MHz. PLL2 is reported locked.
I am using the force holdoff register to enable the clock output.
I am trying to achieve a 400MHz DACCLK and 6.25MHz SYSREF. There is a DACCLK but no SYSREF.
Do I need PLL1 lock to enable SYSREF ?
DAC38J84_ConfigRegs.cfg
