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Tool/software:
I am trying to achieve a continuous SYSREF signal for debugging my JESD204B links.
The PLL1 isn't locked at the moment, but the PLL2 is sourced from a stable signal generator at 120MHz. PLL2 is reported locked.
I am using the force holdoff register to enable the clock output.
I am trying to achieve a 400MHz DACCLK and 6.25MHz SYSREF. There is a DACCLK but no SYSREF.
Do I need PLL1 lock to enable SYSREF ?
DAC38J84_ConfigRegs.cfg
Hi Phil,
Can you attach a .tcs configuration file please.
What is the input clk frequency for CLKinX?
Please refer to page 39 of DS for more information regarding up SYSREF. 
Section 9.3.2.1 goes into detail regarding an example and setting up.
Best regards,
Vicente
