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Hi team
Customer used the 941AS splitter mode but could not output the picture. Besides, they used Independent 2:2 mode and successfully to output the SoC 1920*720 picture and they connected the DSI only with 941AS DSI port0. If they switch the mode to Symmetric Splitting- Left/Right, they monitored the 948 (DES side) output lane 3 and found that there was no Hsync and Vsync waveform, but there was a clock output from 948 which was 1/2 of the DSI clock and this was proper.
Here I listed customer register configuration from 941AS:
unsigned char ds90ub941_reg_init[INIT_MAX_REG][2]=
{
{0x01,0x0c},
{0x56,0x80},
{0x1E,0x01},
{0x32,0xc0},//
{0x33,0x03},//
{0x4f,0x8c},
{0x5b,0x07},
{0x40,0x04},
{0x41,0x05},
{0x42,0x0e},
{0x01,0x00},
};
Could you please help to check when customer would like to use Symmetric Splitting - left/right setting, what configuration should be set to 941AS to successfully output the SoC picture?
Hi Ben,
Sure I will let customer to have a try for these commands. Besides, Customer has requirement of using DSI clock in 941AS splitter mode for 2 different timing specs displays, so please help us to generate the script for us or to check whether the splitter mode could work for these 2 displays:
display A timing:
display B timing:
Here is the topology and signal transport link:
Customer uses single DSI port 0 input for 941AS and splitter mode to output 2 display with above timings. In my opinion splitter mode need the same Htotal*Vtotal right? Please double check how could we implement this solution with your script, thank you.
Hi Ben
1. Let me clarify the scenario again. We only have 2 displays: A and B therefore I clarify the topology and each of the screen use 1920*720@60hz resolution.
Here is our configuration for 941AS register which followed your 941AS splitter mode documents chapter 7 instruction to configure the splitter mode:
Splitter Mode Operations With the DS90Ux941ASQ1.pdf
Following is the timing we set to DSI port 0 from 8155 which is ok with both the A and B displays:
The phenomenon is the 2 screens both failed to output the picture from SoC, just black screens.
Dump registers for 941AS after running the splitter configuration when black screens happen:
(Left number is reg address and right one is reg value)
2. However, displays could work in 941AS independent 2:2 mode, here I also listed the configuration we have done:
Please help us to check what configuration we wrongly/missing configured quickly, the actual application scenario is:
DSI continuous clock mode, DSI single port0, 941AS splitter mode with two 948s.
Wait for your response and please tell us how to successfully configure the 941AS splitter mode, thank you very much!
Hi Zirui,
Under the premise of normal Replicate mode, we do not change anything, only switch to splitter mode (0x5B,0x07)
Are you only doing this to switch to splitter mode? There are more configurations that need to be done, as can be seen in the script I sent you. Left/Right 3D processing must be enabled, among other configurations. Please incorporate the necessary configurations into your script. These can be found in the script I provided, or even in the Splitter Mode Operations with the DS90Ux941ASQ1 appnote. Here is a snip from this appnote:
If you add these configurations (corresponding to your timing of course), splitter mode should work.
Also, for proper operation of Left/Right 3D format, the images must have identical video format (lines, pixels, blanking). As discussed before, the pixel clock must be twice the frequency needed for a single image. This means the timing from the DSI input must have 2*(Hactive, Hfront porch, Hback porch, Hsync).
Regards,
Ben
