Part Number: DS90UB941AS-Q1
// config SER ub941 0x0c 0x1E 0x03 // Select FPD-Link III Port 0 and Port1 0x0c 0x66 0x1A 0x0c 0x67 0x03 // M = 3 0x0c 0x66 0x03 0x0c 0x67 0x19 // N = 25, set CLK= 800*3/25 = 96M 0x0c 0x01 0x08 // Disable DSI 0x0c 0x1E 0x01 // Select FPD-Link III Port 0 0x0c 0x4F 0x8C // Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 0 0x0c 0x5b 0x07 // Force split mode 0x0c 0x56 0x80 // port0 dsi continue clock 0x0c 0x32 0x80 // Set the line size to 1920(LSB) 0x0c 0x33 0x07 // Set the line size to 1920 (MSB) 0x0c 0x1E 0x01 // Select FPD-Link III Port 0 0x0c 0x36 0x00 // Set crop start X position to 0 (LSB) 0x0c 0x37 0x80 // Set crop start X position to 0 (MSB) and enable cropping 0x0c 0x38 0x7F // Set crop stop X position to 1919 (LSB) 0x0c 0x39 0x07 // Set crop stop X position to 1919 (MSB) 0x0c 0x3A 0x00 // Set crop start Y position to 0 (LSB) 0x0c 0x3B 0x00 // Set crop start Y position to 0 (MSB) 0x0c 0x3C 0xCF // Set crop stop Y position to 719 (LSB) 0x0c 0x3D 0x02 // Set crop stop Y position to 719 (MSB) 0x0c 0x1E 0x02 // Select FPD-Link III Port 1 0x0c 0x36 0x00 // Set crop start X position to 0 (LSB) 0x0c 0x37 0x80 // Set crop start X position to 0 (MSB) and enable cropping 0x0c 0x38 0x7F // Set crop stop X position to 1919 (LSB) 0x0c 0x39 0x07 // Set crop stop X position to 1919 (MSB) 0x0c 0x3A 0x00 // Set crop start Y position to 0 (LSB) 0x0c 0x3B 0x00 // Set crop start Y position to 0 (MSB) 0x0c 0x3C 0xCF // Set crop stop Y position to 719 (LSB) 0x0c 0x3D 0x02 // Set crop stop Y position to 719 (MSB) 0x0c 0x40 0x04 // Select DSI Port 0 digital registers 0x0c 0x41 0x05 // Select DPHY_SKIP_TIMING register 0x0c 0x42 0x42 // Write TSKIP_CNT value for 577 MHz DSI clock frequency 0x0c 0x40 0x10 // Init DSI clock settings (section 10.2 of the datasheet) 0x0c 0x41 0x86 0x0c 0x42 0x0A 0x0c 0x41 0x94 0x0c 0x42 0x0A 0x0c 0x1e 0x01 // passthrough all i2c dev to soc side 0x0c 0x17 0x9e 0x0c 0x1e 0x02 // passthrough all i2c dev to soc side 0x0c 0x17 0x9e 0x0c 0x1e 0x04 0x0c 0x17 0x9e delay(50ms) // config DES1 ub948 0x34 0x01 0xff delay(5ms) 0x34 0x1d 0x13 0x34 0x26 0x15 0x34 0x27 0x15 0x34 0x41 0x1f 0x34 0x4b 0x0a // config DES1 ub948 0x0c 0x01 0xff delay(5ms) 0x0c 0x56 0x80 0x0c 0x01 0x00 0x0c 0x64 0x00 0x0c 0x65 0x00 // config BL1 0x15 0x03 0xff // set brightness value 0x15 0x04 0x01 // enable backlight 1 // config BL1 0x6B 0x03 0xff // set brightness value 0x6B 0x04 0x01 // enable backlight 2 // SER ub941 0x0c 0x01 0x00 //enable DSII
Mode Info:1. Host SoC: Qcom SA8155
2. Backlight1 and Backlight 2 is on
3. DSI clock is continues
4. Host config image size is 3840x720@60fps
5. Host config timing：
<Group id="Active Timing">
<HorizontalActive units="Dot Clocks">3840</HorizontalActive>
<HorizontalFrontPorch units="Dot Clocks">64</HorizontalFrontPorch>
<HorizontalBackPorch units="Dot Clocks">128</HorizontalBackPorch>
<HorizontalSyncPulse units="Dot Clocks">64</HorizontalSyncPulse>
<HorizontalSyncSkew units="Dot Clocks">0</HorizontalSyncSkew>
<HorizontalLeftBorder units="Dot Clocks">0</HorizontalLeftBorder>
<HorizontalRightBorder units="Dot Clocks">0</HorizontalRightBorder>
<VerticalActive units="Dot Clocks">720</VerticalActive>
<VerticalFrontPorch units="Lines">36</VerticalFrontPorch>
<VerticalBackPorch units="Lines">18</VerticalBackPorch>
<VerticalSyncPulse units="Lines">8</VerticalSyncPulse>
<VerticalSyncSkew units="Lines">0</VerticalSyncSkew>
<VerticalTopBorder units="Lines">0</VerticalTopBorder>
<VerticalBottomBorder units="Lines">0</VerticalBottomBorder>
<InvertDataPolarity>False</InvertDataPolarity>
<InvertVsyncPolairty>False</InvertVsyncPolairty>
<InvertHsyncPolarity>False</InvertHsyncPolarity>
<BorderColor>0x0</BorderColor>
</Group>
Hi TI team:
Could you please help me check the setting of ub941 is right? and how to debug this case？
