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Original question:

DS90UB941AS-Q1: Symmetric Splitting – Left/Right setting questions

DS90UB941AS-Q1: Symmetric Splitting(Left/Right 3D Format) – Panel not display

? ?
Prodigy 10 points
Part Number: DS90UB941AS-Q1

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// config SER ub941
0x0c 0x1E 0x03 // Select FPD-Link III Port 0 and Port1
0x0c 0x66 0x1A
0x0c 0x67 0x03 // M = 3
0x0c 0x66 0x03
0x0c 0x67 0x19 // N = 25, set CLK= 800*3/25 = 96M
0x0c 0x01 0x08 // Disable DSI
0x0c 0x1E 0x01 // Select FPD-Link III Port 0
0x0c 0x4F 0x8C // Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 0
0x0c 0x5b 0x07 // Force split mode
0x0c 0x56 0x80 // port0 dsi continue clock
0x0c 0x32 0x80 // Set the line size to 1920(LSB)
0x0c 0x33 0x07 // Set the line size to 1920 (MSB)
0x0c 0x1E 0x01 // Select FPD-Link III Port 0
0x0c 0x36 0x00 // Set crop start X position to 0 (LSB)
0x0c 0x37 0x80 // Set crop start X position to 0 (MSB) and enable cropping
0x0c 0x38 0x7F // Set crop stop X position to 1919 (LSB)
0x0c 0x39 0x07 // Set crop stop X position to 1919 (MSB)
0x0c 0x3A 0x00 // Set crop start Y position to 0 (LSB)
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
I

Mode Info:1. Host SoC: Qcom SA8155

2. Backlight1 and Backlight 2 is on

3. DSI clock is continues

4. Host config image size is 3840x720@60fps

5. Host config timing：

<Group id="Active Timing">
 <HorizontalActive units="Dot Clocks">3840</HorizontalActive>
 <HorizontalFrontPorch units="Dot Clocks">64</HorizontalFrontPorch>
 <HorizontalBackPorch units="Dot Clocks">128</HorizontalBackPorch>
 <HorizontalSyncPulse units="Dot Clocks">64</HorizontalSyncPulse>
 <HorizontalSyncSkew units="Dot Clocks">0</HorizontalSyncSkew>
 <HorizontalLeftBorder units="Dot Clocks">0</HorizontalLeftBorder>
 <HorizontalRightBorder units="Dot Clocks">0</HorizontalRightBorder>
 <VerticalActive units="Dot Clocks">720</VerticalActive>
 <VerticalFrontPorch units="Lines">36</VerticalFrontPorch>
 <VerticalBackPorch units="Lines">18</VerticalBackPorch>
 <VerticalSyncPulse units="Lines">8</VerticalSyncPulse>
 <VerticalSyncSkew units="Lines">0</VerticalSyncSkew>
 <VerticalTopBorder units="Lines">0</VerticalTopBorder>
 <VerticalBottomBorder units="Lines">0</VerticalBottomBorder>
 <InvertDataPolarity>False</InvertDataPolarity>
 <InvertVsyncPolairty>False</InvertVsyncPolairty>
 <InvertHsyncPolarity>False</InvertHsyncPolarity>
 <BorderColor>0x0</BorderColor>
</Group>
Hi TI team:
Could you please help me check the setting of ub941 is right? and how to debug this case？

  • 0
    TI__Mastermind 25765 points

    Hello,

    I will look over this script to make sure it is correct. In the meantime can you confirm a few things:

    • Are you trying to use patgen, or end to end?
    • What is the full timing being used?

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    Prodigy 10 points

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    /*
    Panel Timing:
    H-width :1920, HFP:32 HBP:64 HVsync:32
    V-height:720, VFP:36 VBP:18 VSync :8
    */
    0x0c 0x1E 0x03 // Select FPD-Link III Port 0 and Port1
    0x0c 0x66 0x04 // Set H-Total 0x800, 2048(1920+32+64+32); V-Total 0x30E, 782(720+36+18+8);
    0x0c 0x67 0x00
    0x0c 0x66 0x05
    0x0c 0x67 0xE8
    0x0c 0x66 0x06
    0x0c 0x67 0x30
    0x0c 0x66 0x07 // Set H-Width 0x780, 1920; V-Height 0x2d0, 720;
    0x0c 0x67 0x80
    0x0c 0x66 0x08
    0x0c 0x67 0x07
    0x0c 0x66 0x09
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Hi Ben:

    use above patgen code, panel1 and panel2  can display color bars; 
    Pattern Generator Timing as above,  Horizonta timing is 1/2 of host.

    SA8155 config full Timing:  
     3840x720@60fps, 

    H-width :3840, HFP:64 HBP:128 HVsync:64 

    V-height:720, VFP:36 VBP:18 VSync :8

  • 0 in reply to ? ?
    TI__Mastermind 25765 points

    Hello,

    I regenerated a script for you. Please try this script to see if there is any improvement:

    Superframe_Crop_3840x720.py
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    # 941AS Superframe config
    # Python script : Superframe_Crop_3840x720
    import time
    UH941AS = 4
    board.WriteI2C(UH941AS,0x01,0x08) #Disable DSI
    # set split mode, left/right 3D image, non-continuous clock mode
    board.WriteI2C(UH941AS,0x1E,0x01) #Select Port0
    board.WriteI2C(UH941AS,0x5B,0x07) #Force Splitter Mode
    board.WriteI2C(UH941AS,0x56,0x80) #Enable conversion of L/R image into alternating pixel image
    board.WriteI2C(UH941AS, 0x4F, 0x8C) #Set 4 lane DSI
    ##### Register 4F code configuration limited to use case of single DSI mode (RX Port 0) and no Altnerate line mode. If you would like to change the mode, please see register 0x4F [6:4] in D/S
    board.WriteI2C(UH941AS,0x1E,0x02) #Select Port1
    board.WriteI2C(UH941AS,0x5B,0x07) #Force Splitter Mode
    board.WriteI2C(UH941AS,0x56,0x80) #Enable conversion of L/R image into alternating pixel image
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    Prodigy 10 points

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    // config patgen
    0c 1E 03
    0c 66 04
    0c 67 00
    0c 66 05
    0c 67 E8
    0c 66 06
    0c 67 30
    0c 66 07
    0c 67 80
    0c 66 08
    0c 67 07
    0c 66 09
    0c 67 2D
    0c 66 0A
    0c 67 20
    0c 66 0B
    0c 67 08
    0c 66 0C
    0c 67 40
    0c 66 0D
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Hi ben;

    I try the setting of  Superframe_Crop_3840x720.py, The phenomenon is the same as before(backlight is on, but panel not display image);

    setting as above.

  • 0 in reply to ? ?
    Prodigy 10 points

    I try config SA8155 output 1920x720 size image ，and config ub941 work in single-link-mode， Panel1 can display image；

    I have a question, what is the difference between split-mode and sing-link mode input formats? I understand it's just the size is different. so, I configure the host side output just to increase the image size and h-porch for split-mode；is or right?

  • 0 in reply to ? ?
    TI__Mastermind 25765 points

    Hi,

    The PCLK and the horizontal timing needs to be twice the size of a single image, yes.

    Can you confirm a couple more things?

    • Is there lock established with the 948s?
    • Patgen with internal timing and external clock works, can you try patgen with external timing and external clock? This will help us to determine where the issue is. It seems to me right now that it may be an issue with the DSI input.

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    Prodigy 10 points

    Hi Ben:

       How to confirm lock established with 948s? measure  lock pin level of 948s? or read which register of 948s?  what's the meaning of lock status ?

       I try patgen with external timing and external clock(change reg 0x64=0x08), panel is not display.

  • 0 in reply to ? ?
    Prodigy 10 points

    Hi Ben：

    There is a few info, please help check:

    1. DSI clock frequency is 576.6 Mhz, whether register（0x3E, 0x3F ）configuration is required？use the default register vaule is or right?
    2. DSI HS-mode is non-burst vsync event, is surport in 941s?

  • 0 in reply to ? ?
    Prodigy 10 points

    Hi Ben:

    There are new phenomena:

    I  try config non_burst_sync_pulse for dsi hs-mode, 

    • patgen with external timing and external clock, panel1 and panel2 can display color bar; 
    • Close patgen, Panel1 and Panel2 also display image, but Panel2 display image conents is same as Panel1(left image  of superframe).
  • 0 in reply to ? ?
    TI__Mastermind 25765 points

    Hi,

    Thank you for the updates, this narrows down the issue significantly. Can you ensure that the DSI source follows the MIPI DSI standard closely, and enables LP-11 during at least one of the BLLP periods of the video frame?

    Can you also check the indirect register 0x2A to confirm the DSI_DTYPE is reported correctly?

    If the DSI source is correctly implementing LP-11 transitions, and the DSI_DTYPE is correct, you may need to check the DSI source with a protocol analyzer. Instructions on how to check these things are described in the DS90UB941AS-Q1 DSI Bringup Guide.

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    Prodigy 10 points

    Hi Ben:

    1. readback register 0x2A (DSI_DTYPE ), value is 0x3E;

    2. indirect register 0x05(TSKIP_CNT) config value is 0x42, (Other values have also been tried).

    3. Measured by oscilloscope, LP11 per frame, continuous clock, fps 60HZ

    4. Check items as described in the documentation DS90UB941AS-Q1 DSI Bringup Guide，No obvious abnormality found .

    Which reasons may cause the following phenomena?

    Phenomena:

    Using the line interleaved source image to test, Panel1 displays odd lines of content,Panel2 shows even lines;but the right half of the source image is not displayed.

     

    sourceimage:sourceImage

    Panel1Panel2

  • 0 in reply to ? ?
    TI__Mastermind 25765 points

    Hi,

    It seems that Alternate line splitting is occurring while Left/Right (Side by Side) Splitting is what is needed. Can you provide a register dump? I would like to check to make sure the device programming reflects the script, as well as check register 0x58 VIDEO_3D_STS to see if video processing errors have been detected.

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    Prodigy 10 points

    reg_dump6.txt
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    UB941S main registers dump:
    reg_addr 0x0 = 0x18
    reg_addr 0x1 = 0x0
    reg_addr 0x2 = 0x0
    reg_addr 0x3 = 0x92
    reg_addr 0x4 = 0x0
    reg_addr 0x5 = 0x0
    reg_addr 0x6 = 0x68
    reg_addr 0x7 = 0x0
    reg_addr 0x8 = 0x0
    reg_addr 0x9 = 0x1
    reg_addr 0xA = 0xAE
    reg_addr 0xB = 0x0
    reg_addr 0xC = 0x57
    reg_addr 0xD = 0x30
    reg_addr 0xE = 0x0
    reg_addr 0xF = 0x0
    reg_addr 0x10 = 0x0
    reg_addr 0x11 = 0x0
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
    reg_setting.txt
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    0c 1E 03
    0c 66 04
    0c 67 00
    0c 66 05
    0c 67 E8
    0c 66 06
    0c 67 30
    0c 66 07
    0c 67 80
    0c 66 08
    0c 67 07
    0c 66 09
    0c 67 2D
    0c 66 0A
    0c 67 20
    0c 66 0B
    0c 67 08
    0c 66 0C
    0c 67 40
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Hi Ben:

    Please check the above dump file and setting file； Restart the machine, the value of register 0x58(VIDEO_3D_STS ) is different, there are one of the following values: 0x03, 0x02, 0x01, 0x00;

    Found a new problem,  when the machine is completely powered off and restarted, i2c write backlight2 will fail probabilistically and backlight2 not on, what is the possible reason？

  • 0 in reply to ? ?
    TI__Mastermind 25765 points

    Hello,

    Based on the VIDEO_3D_STS errors, it seems that the DSI source is not transmitting the correct timing to the 941AS. Do you have the capability to check the DSI source with protocol analyzer?

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    Prodigy 10 points

    Yes, this is difficult for us，and we have no analyzer available to analyze high speed timing。

  • 0 in reply to ? ?
    TI__Mastermind 25765 points

    Hi,

    Okay, I believe I can assist in giving instructions on how to extract the timing parameters, but I will need to give these instructions over private message since this is a public thread.

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    TI__Mastermind 25765 points

    Hello,

    I am closing this thread for now as we have taken this discussion to private message. Please post here again if additional support is needed.

    Please be noted that the E2E support forums will undergo maintenance from Sept. 28 to Oct. 2, hence it will not be available during this time. If you need design support during this time, please contact your TI representative

    Normal E2E support should be back by Monday, Oct. 3.

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    Prodigy 10 points

    Hi Ben:

    Thank you very much for your support；Now， Split-Mode display can display correctly；

    Because the dsi source  is abnormal; when the configuration width is greater than 2560, the SA8155 display module will separate the image buffer and use two LMs to process the image buffer, which will eventually cause the dsi output to be non-surperframe source.