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Hi team：
I used the 941AS splitter mode but could not output the picture. Besides, I try config SA8155 output 1920x720 or 960x720 size image ，and config ub941 work in single FPD-LINK Transmitter mode， Panel0 can display image
More Info:
1. Host SoC: Qcom SA8155
2. Host Soc output timing info:
1920*720@60
Hey Alex,
I need more information about your system configuration. If you are running 2 displays with resolution of 1920x720 with a superframe of 3840x720 then you can use the left/right splitting method explained in the datasheet (8.4.4.1 Left/Right 3D Format Support)
A few things we need to know is your DSI source config:
DSI Continuous Clock Mode:
DSI input mode:
DSI PORT:
DSI number of LANES:
I attached a script for 1920x720 with PCLK = 108 per display and Superframe 3840x720 with PCLK 216 Mhz and symmetric split application with 941AS for reference.
There are different formats for the input video (Left/Right 3D format, Alternate Line 3D format, and Alternate Pixel 3D format). I will attach an app note that gives more information on the Ux941 splitter mode operations.
App note: Link
Regards,
Fadi A.
Hi Alex,
Continuous DSI clock mode
Yes, that's what I have in the script
Single-DSI mode
Yes, that's what I have in the script
DSI Input port0
Yes, that's what I have in the script
4 lanes
Yes, that's what I have in the script
I try config SA8155 output 1920x720 size image ，and running 2 displays with resolution of 960x720, but can not display image.
Is your superframe image 1920x720 and your 2 separate panels each one is 960x720? If that's the case can you try the modified script below.
The first script I sent you is configured for a side by side superframe (3840x720) running at PCLK = 216 MHz the superframe then gets cropped into 2 videos - each video has a resolution of 1920x720 at 108 MHz.
Modified Script - This script is for a side by side superframe (1920x720) running at PCLK = 108 MHz the superframe then gets cropped into 2 videos - each video has a resolution of 960x720 at 54 MHz.
If this isn't what you are looking for, please send me a block diagram of the configuration you need, thanks.
Regards,
Fadi A.
Hi Fadi：
When you say it works in single FPD-Link Transmitter mode, are you talking about Internal PATGEN from 941AS to display or is does it work when using the SoC: Qcom SA8155 video output ?
What is the exact timing you were using here for the working case?
I've tested it both ways： PATGEN and SoC: Qcom SA8155 video output
Difference between 0x8 and 0xC is toggling bit2 which selects the timing for the internal generated pattern. In Independent 2:2 mode, this controls the selected FPD-Link III port. which you could select through register 0x1E.
Please refer to the picture below for setting of PATGEN. 0x1e = 0x1
0x5b = 0x1 is forcing single FPD-Link on Port0 only and disabling Port1 so that makes sense that you would only see display on panel0.
In your case, you need to set 0x5B = 0x07 for Splitter mode.
Yes, you right. I just want to test whether it is the problem of SOC: video output. According to the current phenomenon, there is no problem with SOC: video output, but we still cannot display it through split mode
Hi Alex,
What Des do you use here?
Can you send me the timing for the working panel?
So you got Patgen from 941 as well as SoC video to work when using a single FPD port0 to display?
Do you have access to ALP ? If no can you download ALP and do you have USB2ANY or Ardvark that you can connect to local I2C of 929?
I can't see this image it's blurry.
Regards,
Fadi A.
Hey Alex,
Can you run this script.
I have 941 and both 948 set to mode_Sel1 = 1 , mode_sel0=1.
Here are the results I got:
Setup:
Output: using a dual panel display, first 948 (port0) connected to left side panel, 2nd 948 (port1) connected to right side panel.
Please try running the splitter script below - this is for internal timing and patgen (colorbar/red) and confirm the following:
1- confirm you have Lock on both Des0 and Des1
2- confirm the output matches the expected image below
output: using a dual panel display, first 948 (port0) connected to left side panel, 2nd 948 (port1) connected to right side panel.
Regards,
Fadi A.
Hi Fadi:
I tried this script and the results are as follows:
The result of Auto-Detect FPD-Link III mode_941AS_1920_720_Per_Panel.py:
1. The screen cannot be displayed using this script
2. Add 0x01 = 0x0 to this script, the screen can display image.
The result of splitter_mode.py:
1. The screen cannot be displayed using this script
2. Add 0x01 = 0x0 to this script, the screen can display image.
Hey Alex,
That is because the DSI is held in reset state at the beginning of the script ... board.WriteI2C(Ser_addr,0x01,0x08) we forgot to release it (0x01 = 0x0)
Looks like the original script did have this release, but I forgot to add it to this one.
Based on these results, this means the internal patgen with internal timing/clk is working as expected which means the issue is coming from the SoC side.
You can further narrow down the issue by doing the following:
1- Run this script - this is set to internal patgen using external timing/CLK from SoC (if this doesn't work then it points to an external timing/CLK issue)
2- Run this script - this is set to internal patgen using internal timing with external CLK (if this doesn't work then it points to an external pixel clock issue)
3- If above isn't enough to help you fix the issue - We have a DSI bring-up guide to debug issues with SoCs please see attached.
5100.DSI Bring up guid (1).pdf
Make sure your SoC timing matches the timing I put into the above script.
Working timing:
For the SoC script you can use this script
Regards,
Fadi A.
Hey Alex,
We need to get a register dump of the 941AS to review it. If possible can you provide the register dump of 941AS and 948? If you could do a dump during the run where you have a single panel0 working vs. when both panels aren't working ?
config SA8155 output 1920x720 size image ，and config ub941 work in attern Generator, set 0x65 = 0xc，Panel0 can display image
if config 941 working in forcing single FPD-Link mode,and SOC video output has not change ,PATGEN work well . Based on these results, i think there is no problem in soc side.
using splitter_mode_internal_timing_externel_clk.py, config soc output 1920x720 size image ,panel can display image
Please confirm that this is the timing that's programmed into the SoC and it's outputting as a superframe 3840x720 image running @ 216.108 mhz?
but using the same timing, why panel can display image when 941 working in inforcing single FPD-Link mode?
If your SoC is sending a 1920x720 image @ 108 Mhz then when you force a single link it will work on port0 because it matches the expected timing coming from the SoC.
Please confirm that this is your system block diagram
Hi Fadi:
There is script: using internal timing clk to display image
Hi Lou,
The following app note will help here with symmetrical splitting as well for reference. Splitter Mode Of 941
After looking at your data, it is not clear what the issue is here. Your script "3840x720 Sym Split Script Superframe 216Mhz" looks correct. It is close to the below proven script also for 3840x720 symmetrical superframe.
Can you try lowering your PCLK? These devices are actually only rated up to 105MHz PCLK, and you are trying 108MHz. Can the blanking size be reduced?
Regards,
Logan
Hey Alex,
I'm still reviewing the register dumps, It could that since the 948 runs at a slower PCLK than 941AS we may need to adjust your PCLK to get it working with your resolution.
948 PCLK Spec:
Let's see if we can get the lower resolution to work with internal patgen using internal timing/clk and we'll move to the next step.
Can you try running this script?
Regards,
Fadi A.
