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Original question:
Hi,
I use C6748 with DDR2, the C6748 is running at 456MHz, whe DDR2 CLK is 156MHz.
And below is my DDR2 chip parameters, the chip is MT47H64M16NF-25E.
And my gel file is attatched.
I tested the throughput of the memory touch, from DDR2 to L1Cache，32KB totally. The average speed is 340MB/s.
My question is:
Q1： Is the DDR2 chip best suitable for C6748? Do you have any suggestion on the DDR2 parameters for better performance? Or do you have any suggested chip?
Q2: Is the configuration in the gel file suitable for this chip MT47H64M16NF-25E? Any better configurations? How to caculation the parameters?
Q3: Is 340MB/s the best result for C6748? Does TI have any benchmark on DDR2 for C6748?
Thank you.
Frank
Hello Frank,
The memory controller on C6748 supports any JESD79-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices. Please see section 6.11 of the datasheet.
You can use the mDDR/DDR2 tool attached to the following application note to check your settings:
Programming mDDR/DDR2 EMIF on OMAP-L1x/C674x
We do not have any DDR benchmarks available. However, there is some data on shared ram access below which should be similar to DDR, minus the DDR refresh and access latency.
The following threads may be useful as well.
https://e2e.ti.com/support/processors/f/791/t/234211
https://e2e.ti.com/support/processors/f/791/t/274688
Regards,
Sahin
Frank
The access size in Sahin's response will depend on the master, the 4,8 bytes etc is CPU load/stores.
The best throughput or utilization for Shared RAM or DDR will come when using the EDMA , as that is when the default access size is the ~ 64 bytes ( EDMA default burst size) for linear memory to memory transfers. With DMA you can get close to 80% utilization of the theoritical max of the Shared RAM or DDR.
Some EDMA throughput data can be found
For CPU load/stores your throughput will be limited by CPU's read/write access size for load/stores, which will not fully utilize the bus. The 32 and 128 byte for ARM and DSP in the table Sahin posted is for "cache line size" accesses.
The throughput will not depend much on the DDR2 memory type etc. Configuration wise just use the timing calculator for DDR that was also provided in Sahin's post.
Regards
Mukul
