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Original question:

C6748 initialising DDR2/mDDR memory controller

TMS320C6748: Best DDR2 chip and best DDR2 configuration for C6748

FrankXu
Genius 3500 points
Part Number: TMS320C6748

Hi,

        I use C6748 with DDR2, the C6748 is running at 456MHz, whe DDR2 CLK is 156MHz.

        And below is my DDR2 chip parameters, the chip is MT47H64M16NF-25E. 

        And my gel file is attatched.

        I tested the throughput of the memory touch, from DDR2 to L1Cache，32KB totally. The average speed is 340MB/s.

       My question is:

       Q1： Is the DDR2 chip best suitable for C6748? Do you have any suggestion on the DDR2 parameters for better performance? Or do you have any suggested chip?

       Q2:   Is the configuration in the gel file suitable for this chip MT47H64M16NF-25E? Any better configurations? How to caculation the parameters?

       Q3:   Is 340MB/s the best result for C6748? Does TI have any benchmark on DDR2 for C6748?

    Thank you.

Frank

       my_c6748.gelMT47H64M16NF-25E.pdf

  • 0
    Genius 3500 points

    Anybody please help!

  • 0 in reply to FrankXu
    TI__Mastermind 27355 points

    Hello Frank,

    The memory controller on C6748 supports any JESD79-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices. Please see section 6.11 of the datasheet. 

    You can use the mDDR/DDR2 tool attached to the following application note to check your settings: 

    Programming mDDR/DDR2 EMIF on OMAP-L1x/C674x

    We do not have any DDR benchmarks available. However, there is some data on shared ram access below which should be similar to DDR, minus the DDR refresh and access latency. 

    The following threads may be useful as well.

    https://e2e.ti.com/support/processors/f/791/t/234211

    https://e2e.ti.com/support/processors/f/791/t/274688

    Regards,
    Sahin

  • 0 in reply to Sahin Okur
    Genius 3500 points

    Hi Sahin,

         Thank you very much for reply.

         I tested the ShareRam throughtput using the same method as I used to test the DDR2:

         touch 32KB data from ShareRam into L1 Cache.(the whole board is rest before test to make sure the data is not in Cache already)

         The result is:

         ShareRam: 567MB/s

         DDR2:        340MB/s

         I am confused:

         Q1: Following the table you give, the ShareRam read speed could be 2.67Bytes/Cycle when ACCESS Size is 128.

                So, I think the throughput should be: 2.67*456M=1217MB/s？Am I right?

         Q2: Do you think my 567MB/s result for ShareRam is reasonable?

         Q3: Why did you say " there is some data on shared ram access below which should be similar to DDR, minus the DDR refresh and access latency. "

         Q4: Do you think my 340MB/s result for DDR2 is reasonable?

         Thank you.

    Frank

  • 0 in reply to FrankXu
    TI__Guru* 83935 points

    Frank

    The access size in Sahin's response will depend on the master, the 4,8 bytes etc is CPU load/stores. 

    The best throughput or utilization for Shared RAM or DDR will come when using the EDMA , as that is when the default access size is the ~ 64 bytes ( EDMA default burst size) for linear memory to memory transfers. With DMA you can get close to 80% utilization of the theoritical max of the Shared RAM or DDR. 

    Some EDMA throughput data can be found 

    For CPU load/stores your throughput will be limited by CPU's  read/write access size for load/stores, which will not fully utilize the bus. The 32 and 128 byte for ARM and DSP in the table Sahin posted is for "cache line size" accesses.

    The throughput will not depend much on the DDR2 memory type etc. Configuration wise just use the timing calculator for DDR that was also provided in Sahin's post.

    Regards

    Mukul

  • 0 in reply to Mukul Bhatnagar
    Genius 3500 points

    Hi Mukul,

          Thank you very much for your help.

          I use the DDR as the main ram to store data and program. So, EDMA is not used in my situation.

          Do you think the 340MB/s is reasonable for the throughput from DDR2 to Cache?

          Thank you.

    Frank

  • 0 in reply to FrankXu
    TI__Guru* 83935 points

    Frank

    Sorry I missed addressing your email. 

    I do not have any additional data from my side and I am not sure how you have created your test and test measurements.

    Make sure if you are expecting cache to give you performance lift, you have the MAR bits set appropriately for Shared RAM and DDR memory. 

    You can try to play around with DDR clock (say run at 100 MHz) to see how it impacts your tests. If you have used the timing configurations looking at code references in gel file etc, i do not expect the DDR settings itself making much difference.

    Regards

    Mukul 

  • 0 in reply to Mukul Bhatnagar
    Genius 3500 points

    Hi Mukul,

            Got it. Thanks so much!

    Frank