The DDR design guidelines outlines all details of power aware SI/PI simulations
that need to be run. The eye mask checks from these power aware simulations are the signoff.

We only provide impedance targets for VDD_CORE. This information can be found under processor specific section "Example:AM62Ax" (starting on page 31) in the following document: www.ti.com/.../sprac76
As noted in the document, rails not listed are not simulated by TI due to low load transients. For more information, see the device-specific EVM layout for example implementation of these rails.
Other rails like the IOs are highly dependent on external peripherals. From the SoC perspective, if you look at the MAX current ratings for the IOs, the total current (after combining all the IOs of the same voltage) is still very low < 350mA so we don't simulate this rails/No data available.
Regarding your other questions related to PET, the supply names are not expected to match with processor (Example AM62A) pin names because the power estimates in the PET are itemized by supply groups. The power supply consolidation for these supply groups match the EVM.

Power Distribution Networks: Implementation and Analysis

Sitara Processor Power Distribution Networks: Implementation and Analysis

https://www.ti.com/lit/pdf/sprac76

High Speed Board design and Signal integrity simulation

https://www.ti.com/lit/pdf/spraar7

https://www.ti.com/lit/pdf/spracn9

https://www.ti.com/lit/pdf/sprabi1

Technical Documents

Collaterals and application notes

https://www.ti.com/product/AM6442#tech-docs

Technical Support

AM6442, AM6441, AM6422, AM6421, AM6412, AM6411 Custom board design - FAQs

Previous E2E threads - Keywords AM64x, AM644X, AM6442, AM6441, AM6422, AM6421, AM6412, AM6411

Starting a new thread

(2) TI E2E support forums

Useful links

Sitara family of processors FAQ master list

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1395812/faq-custom-board-hardware-design---master-complete-list-of-faqs-for-all-sitara-processor-am62x-am64x-am243x-am335x-families

Other FAQs

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1347060/faq-am6442-am6441-am6422-am6421-am6412-am6411-custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am64b-schematics

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1337853/faq-am6442-am6441-am6422-am6421-am6412-am6411-custom-board-hardware-design---design-and-review-notes-for-reuse-of-tmds64evm-schematics

SOC POH
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1492996/am620-q1-the-definition-of-power-of-hour-for-automotive-grade/5736233#5736233

Notes

Always ensure you are using the latest version of the documentation.
Check the product folder regularly for the latest version.
On Ti.com, device product folder page, there is a "Notifications" button. Registering here enables automatic notification of device document changes.
If you have any queries or clarification, use E2E to find similar queries or ask a new question

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 1 year ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 204730 points

Hi Board designers,

Configuring Hysteresis

Data sheet

6.3.10 GPIO
6.3.10.1 MAIN Domain
Table 6-35. GPIO0 Signal Descriptions

(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.

6.3.10.2 MCU Domain
Table 6-37. MCU_GPIO0 Signal Descriptions

TRM

5.1.1.3.1.1 Pad Configuration Registers
The pad configuration registers are used to configure most of the device pads. Each pad configuration register
(PADMMR_PADCONFIG0 to PADMMR_PADCONFIG181) is assotiated only with one pad and has bits as
described in Table 5-4.

Regards,

Sreenivasa

+1 Kallikuppa Sreenivasa over 1 year ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 204730 points

Hi Board designers,

Inputs regarding board simulation

Refer below for the AC Impedance plot for VDD_CORE.

The board has undergone full split lot validation with this combination of filtering/decaps.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 7 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 204730 points

Hi Board designers,

Inputs regarding Package shelf life

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1520415/am625-package-shelf-life

Please refer below links

https://www.ti.com/support-quality/quality-policies-procedures/product-shelf-life.html

https://www.ti.com/support-quality/faqs/product-shelf-life-faqs.html

https://www.ti.com/packaging/docs/mslsearch.tsp?OPN=AM6254BTGFHIAMCRQ1&searchSelected=devpartno&searchkey=AM625#divline

https://www.ti.com/support-quality/reliability/reliability-home.html

https://www.ti.com/lit/an/spraby1a/spraby1a.pdf

https://www.ti.com/lit/pdf/snoa550

https://www.ti.com/lit/an/slva840/slva840.pdf

/cfs-file/__key/communityserver-discussions-components-files/791/Baking-Procedure.pdf

(+) AM62P: Air Humidity for Storage and Operation - Processors forum - Processors - TI E2E support forums

I got the ask from a customer if we define the storage air humidity and the air humidity in operation for the AM62P?

I guess not, but I wanted to doublechekc with you.

Also, this is the requirements they are asking for:

Storage air humidity: 30% to 95% RH
Air humidity in operation: 30% to 95% RH

Prior to board assembly but removed from sealed packaging -> device is specified as MSL3, rated for 168hrs exposure at ≤30°C/60%RH ambient conditions without a re-bake being required before board assembly.

We have no spec for operational humidity specification, but device completed and passed relevant qualification at MSL3 moisture precondition + 1000hrs 85°C/85%RH THB (Temperature, Humidity, Bias) per standard JEDEC test conditions

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 2 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 204730 points

Hi Board designers,

Inputs regarding maximum clamping force

(+) AM2432: Maximum Allowable Value of Mechanical Pressure (Clamping Force) to the Top of Package (ALV) - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

AM2432: Maximum Allowable Value of Mechanical Pressure (Clamping Force) to the Top of Package (ALV)

This is in our FCBGA app note (pg 52). It looks like TI’s recommendation is 0.015 lbf per BGA ball.

That same section has some details regarding heat sinks, but I’m not seeing anything too specific. Generally, the customer defines which TIM they should use as well as the design of the heat sink, so I think we can only give them pretty generic guidance.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 1 month ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 204730 points

Hi Board designers,

Inputs regarding weight and material content

https://www.ti.com/materialcontent/home

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 1 month ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 204730 points

Hi Board designers,

Inputs related to PCB selection.

(+) AM2431: Why a substrate with Tg above 170 °C is used - Processors forum - Processors - TI E2E support forums

The TMDS234EVM uses HiTg material(Iteq IT180A) with a glass transition temperature (Tg) of 170 °C or higher.
Could you please explain why a substrate with Tg above 170 °C is necessary?

Generally, I assume it’s for heat resistance and rigidity, but since this is a microcontroller board, it shouldn’t generate much heat, so I expect it’s to prevent warping.
I’d like to know if there are any other reasons. Because the material is hard, drilling and similar processes may have limitations. When looking ahead to mass production, I want to identify if there are any restrictions.

I consolidated inputs from the experts. Looks like the selection is mainly influenced by Cost, availability and performance.

Expert 1
The reason for selecting IT180A was purely based on cost, availability and performance. I don’t recall Tg ever being mentioned in driving the material selection.
The question was asked with regards to cost vs performance trade-offs for different materials. IT180A outperforms something like 370HR on both fronts.

Expert 2
Seemed like 3P was able to easily source IT180A at the various fab vendors they utilize – I thought that was mostly why we started using it in Sitara MCU.

Lower layer count, lower-power (lower operating temperature) boards, without HDI construction, won’t really see a clear benefit to high Tg substrates. Higher Tg is a more precise substrate to fabricate with it doesn’t warp as much as low Tg glass. You also can get more heat cycles out of it for rework without delaminating the layers because the coefficient of thermal expansion (CTE) is so much lower. It also eats via drill bits faster because of those properties. So if cost isn’t an issue, I would still recommend a high Tg material. I prefer the Isola 370HR products if we can get them though since they seem more well documented.

Most automotive sensors are also hermetically sealed assemblies in a high temp environment, so the substrate operating temperature can get to a significant percentage of the low Tg limits (125C…etc). So if we do something in the automotive space, or extended industrial range, might be a good idea to keep high Tg since customers will probably use high Tg too.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 1 month ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 204730 points

Hi Board designers,

Inputs related to E3 design files

SK-AM64: PCB revision E3 (PROC100E3) Design File Package

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 1 month ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 204730 points

Hi Board designers,

Inputs related to device package drawing

Information related to package dimensions
Example: www.ti.com/.../TMS320C6416
FCBGA GLZ Plastic Grid Array 532
www.ti.com/.../searchtipackages.tsp
www.ti.com/.../mpbg175e.pdf
The dimension document mentions ASME-Y14.5-1994 for tolerance
Can you please help to identify or provide the minimum pad size
www.ti.com/.../packaging-terminology.html
www.ti.com/.../SMT-application-notes.html
www.nxp.com/.../AN13656.pdf
www.ti.com.cn/.../szza005.pdf
450um is the SMO in the substrate drawing, so I do agree that we should be recommending a 450um PCB pad size.
For reference, that is typically the pad size we use for 0.8mm pitch. If you look at other 0.8mmp devices (ex. ANF or AMB), we recommend a 450um PCB pad size

(+) TMS320C6416T: TMS320C6416TB : Layout Queries - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 27 days ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 204730 points

Hi Board designers,

Inputs related to PCB material selection

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1592195/am2431-why-a-substrate-with-tg-above-170-c-is-used

The TMDS234EVM uses HiTg material(Iteq IT180A) with a glass transition temperature (Tg) of 170 °C or higher.
Could you please explain why a substrate with Tg above 170 °C is necessary?
Generally, I assume it’s for heat resistance and rigidity, but since this is a microcontroller board, it shouldn’t generate much heat, so I expect it’s to prevent warping.
I’d like to know if there are any other reasons. Because the material is hard, drilling and similar processes may have limitations. When looking ahead to mass production, I want to identify if there are any restrictions.
their main question is if there is a restriction to select Tg of PCB rather than the rigidity if their use case does not expect much high temperature with considering Ta and Pd.

Expert 2
Seemed like 3P was able to easily source IT180A at the various fab vendors they utilize – I thought that was mostly why we started using it in Sitara MCU.

Regards,

Sreenivasa