Package pad diameter and substrate pad dimension
AM64x -> ALV pkg : ball diameter 0.5mm : substrate pad 0.45mm
The recommendation is 1:1 ratio between PCB pad and substrate pad.

Schematic Review Checklist

AM64x/AM243x Schematic Review Checklist (Rev. B)

DDR Board Design and Layout Guidelines

AM64x/AM243x DDR Board Design and Layout Guidelines (Rev. A) (ti.com)

Target impedance

Impedance target values for VDD_CORE on AM64x

Low freq (< 1MHz): 15 mOhm

Mid freq (1 < 20MHz): 35 mOhm

High freq (20 < 50 MHz): 35 mOhm

This is valid for either of the core voltage values. We do not provide target impedance values for other rails on AM64x.

Power Architecture

Powering the AM64x with the TPS65220 or TPS65219 PMIC

https://www.ti.com/lit/an/slvafe9/slvafe9.pdf

Power Distribution Networks: Implementation and Analysis

https://www.ti.com/lit/an/sprac76f/sprac76f.pdf

Design Simulation files

https://www.ti.com/product/AM6442#design-tools-simulation

Simulation files provided includes IBIS, IBIS-AMI, BSDL, Thermal model and power-estimation tool (PET)

IBIS model

https://www.ti.com/lit/zip/sprm730

Thermal model attached in case the thread is not accessible.0268.sprm773a.zip

(23) AM6442: Ansys Compatible Thermal Model - Processors forum - Processors - TI E2E support forums

0268.sprm773a.zip

High Speed Board design and Signal integrity simulation

https://www.ti.com/lit/an/spracn9d/spracn9d.pdf

https://hands.com/~lkcl/ddr3/sprabi1a.pdf

https://www.ti.com/lit/an/spraar7i/spraar7i.pdf

Technical Documents

Collaterals and app notes

https://www.ti.com/product/AM6442#tech-docs

Technical Support

AM6442, AM6441, AM6422, AM6421, AM6412, AM6411 Custom board design - FAQs

Previous E2E threads - Keywords AM64X, Am644X, AM6442, AM6441, AM6422, AM6421, AM6412, AM6411

Starting a new thread

(2) TI E2E support forums

Notes

Always ensure you are using the latest version of the documentation.
Check the product folder regularly for the latest version.
On Ti.com, device product folder page, there is a "Notifications" button. Registering here enables automatic notification of device document changes.
If you have any queries or clarification use E2E to find similar queries or ask a new question

0 Kallikuppa Sreenivasa 4 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 158559 points

Hi Board designers,

Configuring Hysteresis

Data sheet

6.3.10 GPIO
6.3.10.1 MAIN Domain
Table 6-35. GPIO0 Signal Descriptions

(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.

6.3.10.2 MCU Domain
Table 6-37. MCU_GPIO0 Signal Descriptions

TRM

5.1.1.3.1.1 Pad Configuration Registers
The pad configuration registers are used to configure most of the device pads. Each pad configuration register
(PADMMR_PADCONFIG0 to PADMMR_PADCONFIG181) is assotiated only with one pad and has bits as
described in Table 5-4.

Regards,

Sreenivasa

+1 Kallikuppa Sreenivasa 4 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 158559 points

Hi Board designers,

Inputs regarding board simulation

Refer below for the AC Impedance plot for VDD_CORE.

The board has undergone full split lot validation with this combination of filtering/decaps.

Regards,

Sreenivasa

Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

Processors

Processors forum

[FAQ] AM6442, AM6441, AM6422, AM6421, AM6412, AM6411 Custom board hardware design – Collaterals to Get started