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Frequent questions

  • [FAQ] DS90UB940-Q1EVM: Test issue

    Part Number: DS90UB940-Q1EVM Other Parts Discussed in Thread: DS90UH940N-Q1 When debugging the ds90ub940 chip, we encountered the following problems. Please help us: 1. Using ds90ub940 official development board and Ti analog launchpad software …

  • [FAQ] DP83869HM: DP83869 in Bridge Mode to connect two MACs

    Part Number: DP83869HM Please refer below thread for register configuration needed. https://e2e.ti.com/support/interface-group/interface/f/interface-forum/911770/dp83869hm-bridge-rgmii-to-sgmii-mac-to-mac-configuration/3385960?tisearch=e2e-sitesearch&keymatch…

  • [FAQ] SN65DSI84: Line Time with the SN65DSI84

    Part Number: SN65DSI84 Other Parts Discussed in Thread: SN65DSI85 , SN65DSI83 What is line time on the SN65DSI83, SN65DSI84, and SN65DSI85?

  • [FAQ] TPS65987D: New USB Type C PD 3.1 Spec enables Extended Power Range up to 240W (EPR)

    Part Number: TPS65987D What is the new USB PD 3.1 spec enabling up to 240W? When is the 240W version of the USB PD 3.1 spec available? What kinds of products are expected to take advantage of higher power levels up to 240W? I have products in…

  • [FAQ] DP83869HM: TSN Compliant

    Part Number: DP83869HM Time Sensitive Networking (TSN) is bouquet of IEEE standards defined to converge the various priority traffic on the same network. Most of the standards have implications on MAC however these standards have two requirements on…

  • [FAQ] DS90UB940N-Q1: does 940N device has status or error flag for CSI output??

    Part Number: DS90UB940N-Q1 Hi team, my customer is asking if 940N has any kind of status register or error flag for MIPI CSI for diagnotics. actually customer hopes to check line time and total line by register of CSI output. does 940N has such…

  • [FAQ] DS90UB941AS-Q1: T_skip setting with Port swap option.

    Part Number: DS90UB941AS-Q1 Hi Team, My customer will use 2:2 independent mode with output DSI_PORT_SEL option. So DSI port 0 would be output to Link lane 1 and DSI port1 would be output to Link lane0. And T_skip setting should be set on each…

  • [FAQ] DS90UB947-Q1: MAPSEL setting for UB947

    Part Number: DS90UB947-Q1 Hi team, My customer want to confirm with team if MAPSEL=0 is for JEIDA mapping format. because they could get attached test result when they follow datasheet information. OLDI mapping test result of 947.pptx so their…

  • [FAQ] DS90UB913A-Q1: Does UB913 support BT 601 format with UB964?

    Part Number: DS90UB913A-Q1 Hi Team My customer is considering to use 913 and 964. they want to know if 913/964 can support BT 601 format 1280x720@30fps with YUV 422 8bit. I think it is not a problem but I want to check with team 1more time for sure…

  • [FAQ] DS90UB947-Q1: Does device enable OLDI port input even Link detect status (0x0c bit[0]=1b'0 ) is low??

    Part Number: DS90UB947-Q1 Hi Team My customer is developing 947 <->948 for CID application. now they met some issue that when they test 947 with their tester display module with 948, 0x0c bit[0] is high and display is OK. but when they test 947…

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