TI E2E support forums
TI E2E support forums
  • User
  • Site
  • Search
  • User
  • E2E™ design support >
  • Forums
    • Amplifiers
    • API solutions
    • Audio
    • Clock & timing
    • Data converters
    • DLP® products
    • Interface
    • Isolation
    • Logic
    • Microcontrollers
    • Motor drivers
    • Power management
    • Processors
    • RF & microwave
    • Sensors
    • Site support
    • Switches & multiplexers
    • Tools
    • Wireless connectivity
    • Archived forums
    • Archived groups
  • Technical articles
  • TI training
    • Tech days
    • Online training
    • Live events
    • Power Supply Design Seminar
  • Getting started
  • 简体中文
  • More
  • Cancel
Interface

Interface

Interface forum

  • Mentions
  • Tags
  • More
  • Cancel
  • Ask a new question
  • Ask a new question
  • Cancel
Texas Instruments (TI) Interface support forum is an extensive online knowledge base where millions of technical questions and solutions are available 24/7. You can search interface IC content or ask technical support questions on everything from ESD protection to interfacing with USB, Ethernet, and HDMI. Find the right solution for your circuit design challenges by using our TI E2E™ support forums that are supported by thousands of contributing TI experts.
Frequent questions
  • [FAQ] How can I ensure a successful PCIe Gen5 design?

    Nicholaus_Malone
    Nicholaus_Malone
    3 Tips for a successful PCIe Gen5 design With PCIe datarates increasing to 32Gbps in the latest PCIe Gen5 specification, PCIe has allowed for data higher throughput than ever before. Unfortunately, higher data rates can also mean more signal integrity…
    • Answered
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] DP83867CR: How to generate free-running 125MHz clock from DP83867?

    Vikram Sharma
    Vikram Sharma
    Part Number: DP83867CR To generate free running clock of 125MHz on the CLKOUT pin of DP83867 (synced with local reference clock on XI pin) : program register 0x0170[12:8] = 01000
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] DP83867CR: How to generate recovered clock using DP83867?

    Vikram Sharma
    Vikram Sharma
    Part Number: DP83867CR To generate clock in sync with the link-partner (recovered clock of 125MHz or 25MHz) on the CLKOUT pin of DP83867 : program register 0x0170[12:8] = 00000 for 125MHz program register 0x0170[12:8] = 00100 for 25MHz Note…
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] ESD and TVS Protection Devices: All Technical Documentation

    Chris Murphy
    Chris Murphy
    Application Notes Protecting Automotive Can Bus Systems from ESD Overvoltage Events ESD and Surge Protection for USB Interfaces Automotive SerDes ESD Protection MSP430 System-Level ESD Considerations (Rev. B)…
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] DP83TD510E: Can we use a transformer instead of Capacitor for AC coupling on the MDI side for DP83TD510?

    Hillman Lin
    Hillman Lin
    Part Number: DP83TD510E Yes, transformer can be used for filtering out the DC signal when the data is passing through the MDI side. In fact, we use transformer to filter out the AC signal in the Power over Data Line (PoDL) application. Here are the…
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] What is the difference between RMII slave signaling and RMII master signaling?

    Hillman Lin
    Hillman Lin
    RMII slave signaling is connecting 50MHz Crystal to two XI pin of the PHY and/or MAC RMII master signaling is connection 25MHz Crystal to one Master and provide a 50MHz reference lock through REF_CLK pin to the XI pin of the slave side. Slave side does…
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] DP83TC812R-Q1: How can I connect PHYs back to back over RMII?

    Hillman Lin
    Hillman Lin
    Part Number: DP83TC812R-Q1 There are two type of mode that RMII can support: RMII normal mode and RMII Repeater mode: RMII normal mode is also known as MAC to PHY RMII connection. This mode is set as default mode in DP83TC812 so it did not need…
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] DP83TC811S-Q1: Why is Slave/Managed mode PHY linking up with Master/Autonomous PHY link partner?

    Gerome Cacho
    Gerome Cacho
    Part Number: DP83TC811S-Q1 Other Parts Discussed in Thread: DP83TC811R-Q1 When using DP83TC811S-Q1 (or DP83TC811R-Q1), and setting the PHY into managed mode as a slave device via bootstrapping settings, if this device is connected to a master link partner…
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] DS90UH949-Q1: Disable HDCP to work with UB Deserializer

    Alex Reid1
    Alex Reid1
    Part Number: DS90UH949-Q1 Hello, My customer would like to use DS90 UH949 -Q1 devices in place of the DS90 UB949A -Q1 to keep production running. In reviewing the details they have the following questions. Can the HDCP function be disabled? If…
    • Answered
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] Why am I getting "clause-45 not supported" and "error-95" errors with PHY drivers?

    Vikram Sharma
    Vikram Sharma
    Possible reason can be : - "phy_read_mmd" and "phy_write_mmd" are not supported in your kernel version (if version is old). Possible solution to be evaluated : - Change "phy_write_mmd" to "phy_write_mmd_indirect" function and do the corresponding…
    • over 4 years ago
    • Interface
    • Interface forum
<>

View FAQ threads
  • Tags
  • RSS
  • More
  • Cancel
  • Suggested Answer

    SN65DP159: SN65DP159 AC Coupling on TMDS Input 0 Locked

    270 views
    1 reply
    Latest 7 months ago
    by David (ASIC) Liu
  • Not Answered

    MAX3243: The communicate issue between MAX3243 and GD75232 0 Locked

    190 views
    2 replies
    Latest 7 months ago
    by Clemens Ladisch
  • Answered

    SN74AUP1T34: Prop Delay 0 Locked

    165 views
    2 replies
    Latest 7 months ago
    by Clemens Ladisch
  • Not Answered

    SN65DSI84: MIPI DSI (CM5 DSI0 – 4 Lane) to 8-Lane LVDS Conversion Using SN65DSI84ZXHR – Design Confirmation. 0 Locked

    216 views
    2 replies
    Latest 7 months ago
    by Ikram Haque
  • Answered

    TL16C752C: Junction Temperature of TL16C752C 0 Locked

    139 views
    2 replies
    Latest 7 months ago
    by Praneeth Rao
  • Answered

    TXS0104V: TXS0104V: Datasheet says abs. max. for OE is 4.6V but operating max. is 5.5V - one of these is wrong 0 Locked

    142 views
    2 replies
    Latest 7 months ago
    by Stephen Goadhouse
  • Not Answered

    XIO2001: Seeking a Pin-to-Pin Drop-in Replacement for [XIO2001IZGU] 0 Locked

    133 views
    1 reply
    Latest 7 months ago
    by Gregory Kobyakov
  • Suggested Answer

    DS90LV048A: DS90LV048A Data in while powered down 0 Locked

    122 views
    1 reply
    Latest 7 months ago
    by Matt Smith
  • Suggested Answer

    DP83869HM: Distance between PHY DP83869 and transformer 0 Locked

    183 views
    1 reply
    Latest 7 months ago
    by Shane Hauser
  • Answered

    TPD1E01B04-Q1: Suggest ESD diode for FPD link 4 0 Locked

    247 views
    3 replies
    Latest 7 months ago
    by McKenzie Eaker
  • Answered

    TVS-RECOMMENDATION-CALC: Un-encrypted Spice model request 0 Locked

    142 views
    1 reply
    Latest 7 months ago
    by Bryan Rodriguez de San Miguel
  • Answered

    DP83TC815-Q1: Looking for SDAA127 document +1 Locked

    352 views
    3 replies
    Latest 7 months ago
    by Gregory Kobyakov
  • Suggested Answer

    TCAN1042H-Q1: How to limit short circuit current during 48V Bus short 0 Locked

    295 views
    3 replies
    Latest 7 months ago
    by Michael Ikwuyum
  • Not Answered

    TUSB212: How to run USB2 model in HSPICE environment 0 Locked

    182 views
    1 reply
    Latest 7 months ago
    by Ryan Kitto
  • Suggested Answer

    DP83TC812S-Q1: Schematic review 0 Locked

    167 views
    1 reply
    Latest 7 months ago
    by Charles
  • Answered

    TMDS171: Regarding the TMDS171 peripheral circuit 0 Locked

    192 views
    3 replies
    Latest 7 months ago
    by David (ASIC) Liu
  • Answered

    SN65LVDS93A: DP (DisplayPort) to LVDS Bridge 0 Locked

    285 views
    2 replies
    Latest 7 months ago
    by Jackson Carmichael
  • Not Answered

    TSB81BA3E: Cross refrence for TSB81BA3IPFP 0 Locked

    111 views
    2 replies
    Latest 7 months ago
    by jack wu
  • Answered

    TDP2004: Some qusetions and schematic review 0 Locked

    191 views
    3 replies
    Latest 7 months ago
    by Jeff YANG
  • Suggested Answer

    SN65HVD233: Surface damage issue 0 Locked

    142 views
    3 replies
    Latest 7 months ago
    by Michael Ikwuyum
<>