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Processors

Processors

Processors forum

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Texas Instruments (TI) Processors support forum is an extensive online knowledge base where millions of technical questions and solutions are available 24/7. You can search processors content or ask technical support questions on Sitara™ processors, digital signal processors (DSP) and automotive processors. Find the right solution for your circuit design challenges by using our TI E2E™ support forums that are supported by thousands of contributing TI experts.
Frequent questions
  • [FAQ] AM62A3-Q1: The MISO and MOSI of the SPI

    Haiming Qu
    Haiming Qu
    Part Number: AM62A3-Q1 Hi TI expert, The SOC AM62A define the standard SPI interface by SPI_CS, SPI_CLK, SPI_D0, SPI_D1. If our slave device need to get MISO and MOSI data line, how will we used the D0 and D1 data line. Dose it programable? Can…
    • Answered
    • over 2 years ago
    • Processors
    • Processors forum
  • [FAQ] AM625/AM623 Custom board hardware design – Reading DEVICE_ID and Unique SOC (CPU) ID

    Kallikuppa Sreenivasa
    Kallikuppa Sreenivasa
    I have the below queries regarding the DEVICS_ID Is there a device ID available that I can read? Can you guide me how to read the device ID? Is the ID unique for each device? Is there an ID that is unique to each device?
    • Answered
    • over 2 years ago
    • Processors
    • Processors forum
  • [FAQ] AM625: Crystal drive strength specifications

    Munan Xu
    Munan Xu
    Part Number: AM625 Hello, Do we have a specification on the max drive strength/ power that AM625 can drive for both the HF crystal as well as 32 KHz oscillator? I didn't see it specified in the data sheet and customer wants to make sure they're within…
    • over 2 years ago
    • Processors
    • Processors forum
  • [FAQ] How to synchronize the PRU IEP timer with Linux system time?

    Nick Saulnier
    Nick Saulnier
    I am using a Sitara processor with a Linux core, a time sync router, and a PRU subsystem (AM62x, AM64x, AM65x). I want to synchronize the Linux system time with an IEP timer in the PRU subsystem. How do I do it? We will use AM64x for this example, but…
    • Answered
    • over 2 years ago
    • Processors
    • Processors forum
  • [FAQ] PROCESSOR-SDK-J7200: How to change/generate the “Eth” configuration for MCAL Ethernet Application from one core to other core.

    Doredla Sudheer Kumar
    Doredla Sudheer Kumar
    Part Number: PROCESSOR-SDK-J7200 Other Parts Discussed in Thread: DRA821 , DRA829 , SYSCONFIG How to change/generate the “Eth” configuration for MCAL Ethernet Application from one core to other core.
    • Answered
    • over 2 years ago
    • Processors
    • Processors forum
  • [FAQ] AM6412: AM64x SoC power supply slew control for 3.3V_SYS using load switch

    Sirui Zhu
    Sirui Zhu
    Part Number: AM6412 Other Parts Discussed in Thread: TPS65219 Hi team, I'm helping my customer design the power part of AM64. For the power supply slew rate control part, it says the slew rate should be controlled under 18mV/us. How should we set…
    • Answered
    • over 2 years ago
    • Processors
    • Processors forum
  • [FAQ] Redundant boot from eMMC boot partitions on AM62x

    Hong Guan64
    Hong Guan64
    1. booting from eMMC boot partition vs UDA partition It is recommended to use eMMC boot partition for user's BootLoader (BL) - eMMC boot partition is designed for bootloader user case - it is possible to write-protect boot0/boot1 as necessary - eMMC boot…
    • Answered
    • over 2 years ago
    • Processors
    • Processors forum
  • [FAQ] AM62A3: Any way to get 2 eMMC interfaces?

    Brad Caldwell
    Brad Caldwell
    Part Number: AM62A3 Hello, Using the AM62A, is there any way to implement two eMMC interfaces? The device has 3 MMC interfaces but the datasheet only shows MMC0 supporting eMMC. We really need a way to get 2 so I'll ask a couple questions from someone…
    • Answered
    • over 2 years ago
    • Processors
    • Processors forum
  • [FAQ] PROCESSOR-SDK-TDAX: How to change input display pipeline in the DSS M2M WB node?

    Brijesh Jadav
    Brijesh Jadav
    Part Number: PROCESSOR-SDK-TDAX The patches shared on below link adds support for DSS memory to memory path in the vision apps and TIOVX. These patches are also integrated SDK8.6. By default, this patch uses VIDL2 pipeline as input pipeline and WB pipeline…
    • Answered
    • over 2 years ago
    • Processors
    • Processors forum
  • [FAQ] TDA4VM: Process OpenVX Graph while simultaneously configuring a camera

    Nikhil Dasan
    Nikhil Dasan
    Part Number: TDA4VM How to configure a camera without affecting the OpenVX graph, while the single cam application graph is running
    • Answered
    • over 2 years ago
    • Processors
    • Processors forum
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