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Frequent questions

  • [FAQ] TDA4VM: Explain IPC Mailbox allocation ?

    Part Number: TDA4VM IPC uses HW mailboxes. Which ones are used, and which ones are still available ?

  • [FAQ] TDA4VM: How to get EB Tresos studio for MCAL development and customer licence ?

    Part Number: TDA4VM How to get EB studio tool for MCAL development and If you want to run the EB Tresos Configurator for TDA4VM MCAL, a customer license is required. How can I obtain this?

  • [FAQ] TMS320C6657: How to run the direct NAND-BOOT example on TI-C6657-EVM without IBL ?

    Part Number: TMS320C6657 Hi, How to run the direct NAND-BOOT example on TI-C6657-EVM without IBL ?

  • [FAQ] PROCESSOR-SDK-AM64X: Licensing of industrial protocols provide in MCU-SDK

    Part Number: PROCESSOR-SDK-AM64X Hi, What is the "TI Commercial" licensing process for Industrial Protocols provided in MCU-SDK package ? Regards

  • [FAQ] PROCESSOR-SDK-AM64X: Flash Programming Options in Mass Production Phase

    Part Number: PROCESSOR-SDK-AM64X Hi, What is the recommended production method of loading in flash device during mass production? Regards

  • [FAQ] AM64X : How to Reset (Warm Reset ) the SOC from Software ?

    Part Number: AM6442 Hello TI experts, I want to make the SOC reset from software. How can I do it? What is the difference between POR (power on reset) and warm reset? This FAQ mainly explains how to Reset the SOC. And what are the registers used…

  • [FAQ] PROCESSOR-SDK-J721E: How to use TR for transfers in McSPI, instead of packet descriptors?

    Part Number: PROCESSOR-SDK-J721E By default, McSPI/SPI Drivers in PSDKRA uses packet descriptors for transferring or for receiving data to/from the SPI slave device. Sometimes it might require to use TR descriptors, because TR supports additional functionalities…

  • [FAQ] AM62A7-Q1: how to connect the pin net VDDSHV4, VDDSHV5, and VDDSHV6 if SD card is not used

    Part Number: AM62A7-Q1 SD cards is not need in our project using AM62A7-Q1. if SD card is not used, how to connect the pin net VDDSHV4, VDDSHV5, and VDDSHV6 of AM62A7-Q1? leave it open or connected directly to VSS or ?

  • [FAQ] EDGE-AI-STUDIO: Edge AI Resources for AM6xA SoCs

    Part Number: EDGE-AI-STUDIO Texas Instruments has a multitude of resources available for machine learning at the edge (Edge AI). These are spread across ti.com, dev.ti.com (TI Developer Zone + Edge AI Studio), and github. The majority of these resources…

  • [FAQ] PROCESSOR-SDK-AM64X: Accessing DDR from PRU-ICSSG

    Part Number: PROCESSOR-SDK-AM64X Other Parts Discussed in Thread: SYSCONFIG Hi, Can you please help me to access DDR from a PRU core? . The information in this FAQ applies to all Sitara processors with a PRU_ICSSG: AM24x, AM64x, AM65x. The example…

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