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Frequent questions

  • [FAQ] PROCESSOR-SDK-TDAX: How to change input display pipeline in the DSS M2M WB node?

    Part Number: PROCESSOR-SDK-TDAX The patches shared on below link adds support for DSS memory to memory path in the vision apps and TIOVX. These patches are also integrated SDK8.6. By default, this patch uses VIDL2 pipeline as input pipeline and WB pipeline…

  • [FAQ] TDA4VM: Process OpenVX Graph while simultaneously configuring a camera

    Part Number: TDA4VM How to configure a camera without affecting the OpenVX graph, while the single cam application graph is running

  • [FAQ] AM6442, AM6441, AM6422, AM6421, AM6412, AM6411 and AM2434, AM2432, AM2431 (ALV, ALX) Custom board hardware design – Queries regarding Crystal selection and clock specifications

    Part Number: AM6442 AM2432 AM6411 AM2431 AM6422 AM6412 AM6421 AM2434 AM6441 Other Parts Discussed in Thread: TMDS64EVM , , AM3352 , AM62A3-Q1 , AM62L , OMAP-L138 , AM62A7 Hi TI Experts, I have the below queries regarding the crystal selection. …

  • [FAQ] AM6442, AM6441, AM6422, AM6421, AM6412, AM6411 and AM2434, AM2432, AM2431 (ALV, ALX) Custom board hardware design – I2C interface

    Part Number: AM6442 Other Parts Discussed in Thread: AM62A7 , AM6412 , AM6422 , , AM2434 , SK-AM64B Hi TI Experts, I have the below queries regarding the I2C interface: Need information on the number of I2C interfaces available Termination of…

  • [FAQ] AM623: Does AM62x support two 4GB DDR?

    Part Number: AM623 Hi, TI Partner Follow data sheet. it describe as below. DDR Subsystem (DDRSS) – Supports LPDDR4, DDR4 memory types – 16-Bit data bus with inline ECC – Supports speeds up to 1600 MT/s – Max addressable range • 8GBytes with DDR4…

  • [FAQ] PROCESSOR-SDK-J721E: How to enable blending operation and two input video pipelines in DSS memory to memory path?

    Part Number: PROCESSOR-SDK-J721E DSS WB path can take input from the overlay manager output and overlay manager in the DSS can take input from two video pipelines and can blend the images and can send it out. In the current PSDKRA6.0, SDK supports only…

  • [FAQ] AM623: SPI DATA MISO/MOSI usage for D0 / D1

    Part Number: AM623 SPI data pins are named as D0 and D1. Where can i find information about the usage regarding in/output or which one is MISO / MOSI?

  • [FAQ] TDA4VL: RGMII not working on MAIN_CPSW2G in SDK 8.5 and SDK 8.6

    Part Number: TDA4VL I want to use RGMII on MAIN_CPSW2G of TDA4VL. The link is up, but I am not able to establish a communication. I can see that Rx is working but Tx is not working.

  • [FAQ] RPMsg: How to add multiple endpoints to a remote core running RTOS?

    I am using RPMsg to communicate from Linux with a remote core running RTOS (e.g., R5F or M4F). I want to define multiple RPMsg endpoints in my remote core software. How do I do that? . This FAQ applies to AM62x, AM62A, AM64x, AM65x, and probably other…

  • [FAQ] TMS320C6678: DDR3 Read write test code (or) How to do DDR3 test on C6678 EVM or K2H EVM board ?

    Part Number: TMS320C6678 Other Parts Discussed in Thread: SYSBIOS Hi Please provide "DDR3 Read write test code" (or) How to do DDR3 test on C6678 EVM or K2H EVM board ?

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