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LMK04828: No SYSREF output

Part Number: LMK04828
Other Parts Discussed in Thread: ADC32J25

Hello,

With the attached TICS Pro configuration, there is no SYSREF output from SDCLKout1.

Also attached is a copy of the schematic.  LMK04828 circuitry is on Sheet 18.

Do I need to drive the SYNC pin (Pin 6) with a pulse or set it high?

Regards,

Andrew

LMK04828b_v071623c.tcs

fibersense_v1p23.pdf

  • Hi Andrew, 

    Sync requires a pulse or toggling SYNC_POL bit. 

    Procedure to setup SYSREF is found on page 40 of DS: 

    The EVM user guide also provides a quick example setting up SYSREF pulses using the default config: 

    Regards, 

    Vicente 

  • Hi Vicente,

    Is SYNC_POL bit the Pin 6 (SYNC)?

    Can we also toggle once? Or do we need to pulse continuously?

    And are there any timing requirements for the toggling or pulses?

    Regards,

    Andrew

  • Hi Vicente,

    SYNC_POL is a register bit in 0x143.  

    Then I would need to do 3 register writes to toggle.

    Could you clarify on the SYNC pin (Pin 6)?  What is it intended for?

    Thank you,

    Andrew

  • Hi Andrew, 
    You're correct. SYNC_POL is a register bit. 
    You can also drive the SYNC pin using a pulse. 

    Performing a SYNC event can be done with either method. 

    Here is more on sync. 

  • With SYNC_POL_INV = 1, the SYNC pin is active low.

    Please let me know otherwise.
    Let us try it.

    Thank you so much

  • For clarification, SYNC_POL = 1 (for active low).  Then I can drive the SYNC pin with an active low pulse.

    Could you confirm if my understanding is correct?

    Thanks again

  • To perform a sync via SPI,
    Toggle SYNC_POL from L -> H and then from H -> L. 

    Regards, 

    Vicente 

  • Your understanding is correct Slight smile

    Regards, 

    Vicente

  • Hi Vicente,

    Understood.  Let us try.

    Regards,

    Andrew

  • Hi Vicente,

    HexRegisterValues_072023a.txt
    Fullscreen
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    0x000090
    0x000010
    0x000200
    0x000306
    0x0004D0
    0x00055B
    0x000600
    0x000C51
    0x000D04
    0x01000F
    0x010155
    0x010255
    0x010301
    0x010422
    0x010500
    0x010670
    0x010711
    0x01080F
    0x010955
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    After writing from 0x0000 thru 0x1FFF, I went thru the SYSREF setup process in Lines 137 and 147

    0x013900
    0x014319
    0x01000F
    0x01080F
    0x013A01
    0x013B2C
    0x014008
    0x014319
    0x013E03
    0x014339
    0x014319

    I may not have rewritten to the every recommended register but I think I addressed all the key steps.

    I still don't seem to see the SYSREF output from SDCLKout1.

    Could you take a look at the registers?

    Thank you,

    Andrew

  • Hi Andrew, 
    I opened up your config and see your VCO0 frequency is out of range: 

    The registers don't seem to add up with what TICs pro exports for this device. 

    can you double check this? If possible can you attach a .tcs file?

    In regards to generating Sysref, it's important you follow all steps outlined. 

    Please note

  • Hi Vicente,

    Here's the TICs pro file that generated the exported registers.

    The VCO0 is 2400 MHz in TICs pro.

    I'll also try again the SYSREF generation.

    Thank you,

    Andrew

    LMK04828b_v072123a.tcs

  • Hi Vicente,

    Would it be possible to receive a TICs pro file with Sysref running?

    Or an example of exported hex file with Sysref generation?

    I would just like to get an idea of how to correctly generate an Sysref signal.

    Thank you,

    Andrew

  • Hi Andrew,

    With the above received config file (LMK04828b_v072123a.tcs), the device is in SYNC mode (SYSREF output is OFF) and all DCLK dividers will reset once the PLL2 is locked.

    To generate the SYSREF in continuous mode, perform the below writes once PLL2 is locked.

    1. 0x144 --> FF

    2. 0x143 --> 11

    3. 0x139 --> 03

    Thanks!

    Regards,
    Ajeet Pal

  • Hi Ajeet,

    In the screenshot you showed above, how should I change the check boxes?

    The yellowed areas look the same as what I provided.

    Thank you,

    Andrew

  • The way we program the LMK04828 is

    • Set everything in TICs Pro
    • "Export hex register values"
    • Add additional commands like the ones you suggested above
    • Copy and pasted the 0x commands to our FPGA code
    • Build an FPGA image and download to the FPGA

    For completeness, 

    • I would like to get the final .tcs
    • Receive additional commands so I can add to the exported register file

    Thanks again!

    In the meanwhile, I will try your suggestions.

    Andrew

  • Hi Ajeet,

    The 8-MHz Sysref is working after following your suggestions!

    Also attached below are the .tcs (which is the same as yours) and the .hex file I used (basically exported from TICs Pro and added your suggested commands after 0x1FFF53

    LMK04828_JESD204B_Config_Cust.tcs

    HexRegisterValues_072423c_ti.txt
    Fullscreen
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    0x000090
    0x000010
    0x000200
    0x000306
    0x0004D0
    0x00055B
    0x000600
    0x000C51
    0x000D04
    0x01000F
    0x010155
    0x010255
    0x010301
    0x010422
    0x010500
    0x010670
    0x010711
    0x01080F
    0x010955
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Thank you so much,

    Andrew

    ps: I would like to keep this for a few more days as I will now try to get the ADC working as well.

    Regards,

    Andrew

  • Hi Ajeet,

    Could you review the schematic?  I've also made notes on the clock related circuits.

    • DCLKOUT2p/n (ADCCLKP/N): On Slide 5, I think ADC32J25 is expecting LVDS.  So should I update the resistors as noted in Slide 2?
    • SDCLKOUT3p/n (SYSREFP/N): the same question here.  Should I update the resistors?
    • DCLKOUT8p/n (PCIE_CLK1P/N): intended for PCIE.  Please let me know if this looks appropriate
    • SDCLKOUT9p/n (PCIE_CLK1P/N): intended for PCIE.  Please let me know if this looks appropriate

    Thanks again,

    Andrew

    notes 072423a.pdf

    4760.fibersense_v1p23.pdf

  • Hi Andrew,

    Glad to know, you are able to get the SYSREF outputs.

    Regarding your schematic, please see below comments:

    • DCLKOUT2p/n (ADCCLKP/N): On Slide 5, I think ADC32J25 is expecting LVDS.  So should I update the resistors as noted in Slide 2?
    • SDCLKOUT3p/n (SYSREFP/N): the same question here.  Should I update the resistors?

    From the ADC datasheet, below are the expected circuits for the LVDS and LVPECL input clocks.

    Your board schematic, shows the termination for LVPECL input format. Hence, you can keep the R412, R415, R418 and R419 as it is and make the LMK04828 DCLKout2 and SDCLKout3 output setting for LVPECL format.

    • DCLKOUT8p/n (PCIE_CLK1P/N): intended for PCIE.  Please let me know if this looks appropriate
    • SDCLKOUT9p/n (PCIE_CLK1P/N): intended for PCIE.  Please let me know if this looks appropriate

    Follow the section 10.4.2 of LMK04828 datasheet, if receiver doesn't have the internal termination, then can keep the 100ohm resistor across the DCLKoutx_P and  DCLKoutx_N. Otherwise keep the 560ohm across them.

    Based on PCIE receiver termination, you can follow the above suggestions.

    Thanks!

    Regards,
    Ajeet Pal