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Clock & timing

Clock & timing

Clock & timing forum

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Texas Instruments (TI) Clock & timing support forum is an extensive online knowledge base where millions of technical questions and solutions are available 24/7. You can search clock & timing IC content or ask technical support questions on everything from clock synchronizers and generators to clock buffers and timers. Find the right solution for your circuit design challenges by using our TI E2E™ support forums that are supported by thousands of contributing TI experts.

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Frequent questions
  • [FAQ] LMK5B33216: Determining impact of supply voltage noise and PSNR specification on output phase noise

    Timothy T
    Timothy T
    Part Number: LMK5B33216 This covers the math to simulate clock output phase noise noise as a result of voltage supply noise using PSNR and then creating a voltage supply noise mask based on your requirements. How to use PSNR data and input voltage…
    • 3 months ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] The What and How of TI DPLLs (What is a DPLL? How does a DPLL work?)

    Jennifer Bernal
    Jennifer Bernal
    Part Number: LMK5B33216 [DPLL Training Slides] The What-How of TI DPLLs_share, e2e.pdf
    • 3 months ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] PLLATINUMSIM-SW: PLL Training Material

    Dean Banerjee
    Dean Banerjee
    Part Number: PLLATINUMSIM-SW Attached is a detailed training on PLL Theory PLL Fundamentals Full Training (Public).pdf
    • 3 months ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] LMK5B33216: How to choose the loop bandwidth for your PLL

    Timothy T
    Timothy T
    Part Number: LMK5B33216 Here's some information on choosing a loop bandwidth for your PLL to optimize noise performance. The presentation starts with some general theory on noise and PLLs, discusses how to pick loop bandwidth for a "PLL/VCO optimized…
    • 3 months ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] TLC555: What are the performance differences expected for TLC555 PCN 20231130002.1?

    Ron Michallick
    Ron Michallick
    Part Number: TLC555 Other Parts Discussed in Thread: , TLC3555-Q1 , TLC3555 Tool/software: PCN 20231130002.1 is the “Qualification of RFAB using qualified Process Technology, Die Revision, Datasheet update and additional Assembly Site/BOM options…
    • Answered
    • 8 months ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] Does TI have crosses for obsolete Analog Devices HMC103x, HMC7xx, HMC8xx PLL family products and other discontinued products such as ADF5610 and HMC987 as per the Product Discontinuance Notice issued by ADI on March 22, 2022?

    Vibhu  Vanjari
    Vibhu Vanjari
    TI’s wide portfolio of RF PLLs & synthesizers features devices that are potential crosses for Analog Devices HMC103x, HMC7xx, HMC8xx PLL family products and other discontinued products such as ADF5610 and HMC987. With most of TI’s RF PLLs & synthesizers…
    • over 3 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] TPL5010: How to disable the watchdog function of TPL5010

    Dong Shen1
    Dong Shen1
    Part Number: TPL5010 Hi all, I am a FAE of TI,now my customer has a watchdog disabled problem, so I synchronously ask you for a solution: Problem Description: the customer's MCU wants to disable the watchdog function during the recording program…
    • Answered
    • over 4 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] Clock Buffers: How to connect the unused pins?

    Kia Rahbar
    Kia Rahbar
    When a pin on my clock buffer is not being used, what is the correct termination?
    • Answered
    • over 5 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] Clock Buffers: Can my buffer handle an input while it is powered off?

    Aaron Black
    Aaron Black
    If my buffer is powered off can an input go into the device without damaging it?
    • Answered
    • over 5 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] RF synthesizers: How to deal with the unused output differential pin in a RF synthesizer?

    Noel Fung
    Noel Fung
    I need single-ended output, how to deal with the unused output differential pin?
    • Answered
    • over 5 years ago
    • Clock & timing
    • Clock & timing forum
>

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  • Not Answered

    Replace Renesas & SiTime Data Center PCIe Clocking Solutions with TI Buffers & Oscillators. 0

    71 views
    0 replies
    Started 6 days ago
    by CP Ong
  • Not Answered

    [FAQ] The What and How of TI DPLLs (What is a DPLL? How does a DPLL work?) 0

    680 views
    1 reply
    Latest 3 months ago
    by Timothy T
  • Suggested Answer

    LMX2594: Effect of SYNC Category on OSCin Frequency 0

    45 views
    4 replies
    Latest 17 minutes ago
    by wenjing cheng
  • Not Answered

    LMK05318: Checksum verification on TICS Pro 0

    7 views
    0 replies
    Started 1 hour ago
    by Christopher Reese
  • Not Answered

    LMK1D2102L: The propagation delay is more than datasheet described(<575ps maximum) 0

    11 views
    0 replies
    Started 2 hours ago
    by Fan Wu
  • Not Answered

    LMK5B12204: Clock drift after Multiple EEPROM writes. 0

    20 views
    1 reply
    Latest 3 hours ago
    by Connor Lewis
  • Not Answered

    NE555: Footprint pad center dimention not matching with datasheet lan pattern 0

    40 views
    3 replies
    Latest 5 hours ago
    by Ron Michallick
  • Not Answered

    LMK62A2-156M: LMK62A2-156M25SIAT is not recommended for new designs alternative 0

    7 views
    0 replies
    Started 5 hours ago
    by Anthony Wong
  • Suggested Answer

    LMX1214: Differences between register settings the datasheet and TICS Pro. 0

    62 views
    5 replies
    Latest 5 hours ago
    by Noel Fung
  • Not Answered

    CDCE6214-Q1: VCCO inputs and 1.8 LVDS signaling 0

    10 views
    0 replies
    Started 6 hours ago
    by Justin Hoffman
  • Suggested Answer

    TPL5010: Need assistance in using TPL1050 0

    79 views
    3 replies
    Latest 8 hours ago
    by Noel Fung
  • Suggested Answer

    LMK6P: LMK6PA15625ADLER as the reference clock for the Stratix 10 E-tile. 0

    41 views
    3 replies
    Latest 8 hours ago
    by Michael Srinivasan
  • Not Answered

    LMK05318B: LMK05318B: DPLL failing to lock to 1 PPS PRIREF input (LVCMOS) using 40 MHz XO (±1 ppm) 0

    7 views
    0 replies
    Started 8 hours ago
    by Adithyan V A
  • Not Answered

    LMX2615-SP: Touchstone/S-Parameter Files 0

    14 views
    1 reply
    Latest 9 hours ago
    by Lucas Pucheta
  • Suggested Answer

    LMK1D2102L: Clarification on LMK1D2102 vs LMK1D2102L: AMP_SEL pin ON/OFF control 0

    20 views
    1 reply
    Latest 9 hours ago
    by Michael Srinivasan
  • Suggested Answer

    LMX2595EVM: How to synchronizing External MCU Trigger with LMX2595 Ramp Mode using Reference Pro 0

    25 views
    1 reply
    Latest 9 hours ago
    by Noel Fung
  • Not Answered

    LMK1C1106: Require flammability details 0

    12 views
    1 reply
    Latest 9 hours ago
    by Michael Srinivasan
  • Suggested Answer

    LMX2572: OSCin requirements 0

    42 views
    3 replies
    Latest 10 hours ago
    by Noel Fung
  • Suggested Answer

    BQ32000: Utilizing the backup supply 0

    23 views
    1 reply
    Latest 10 hours ago
    by Noel Fung
  • Suggested Answer

    TXB0102: Design Query 0

    215 views
    10 replies
    Latest 10 hours ago
    by Jack Guan
>