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Frequent questions

  • [FAQ] DP83TD510E-EVM: How to use ping and iperf between two PCs through 510EVM Link?

    Part Number: DP83TD510E-EVM ping&iperf_510.ppt

  • [FAQ] DP83826E: How does pin 29 on DP83826 act depending on strap mode?

    Part Number: DP83826E DP83826 in Enhanced mode has a pin which is GPIO, pin 29. This pin can be an LED or can be used as CRS. When PHY is set in RMII mode, this pin can be reprogrammed to be LED or CRS. When MII is strapped, this pin is forced to be CRS…

  • [FAQ] DP83822I: How to use RMII repeater mode in DP83822?

    Part Number: DP83822I Could someone guide me on how to use DP83822 for RMII repeater mode?

  • [FAQ] DP83822I: Link up debug with DP83822

    Part Number: DP83822I

  • [FAQ] DP83822I: 822/826 Odd Nibble Detection disable for EtherCAT application

    Part Number: DP83822I For 822/826 PHYs, Odd Nibbles Detection register need to be disable in order to prevent unexpected link loss in EtherCAT application. DP83826PHY: Odd Nibble Detection could be disable by strap 1 CLKOUT/LED1 pin in enhanced…

  • [FAQ] Can Auto-negotiation link up with Force mode on 100mbps?

  • [FAQ] DP83822IF: Fiber Link Status

    Part Number: DP83822IF Other Parts Discussed in Thread: DP83822HF , The DP83822IF and DP83822HF are the fiber capable variants of the DP83822. Bit 2 in Register 0x0001 indicates link status for both Copper and Fiber modes of operation. In copper mode…

  • [FAQ] Extended Register Space Access for Ethernet PHYs

    Our Ethernet PHYs have a standard set of registers, 0x0-0x1F, that can be accessed in a straight forward fashion. Registers beyond 0x1F require a different approach to access. This FAQ is intended to provide a few examples on how to read/write these…

  • [FAQ] SN65DSI86: SN65DSI86 Resolution Guide

    Part Number: SN65DSI86 What display resolution will the SN65DSI86 support?

  • [FAQ] DP83867E: What is the default mode of RGMII when using DP83867, shift or align?

    Part Number: DP83867E When bootstrapped to be in RGMII mode, DP83867 will be in shift mode by default; not align mode. The modes will be corroborated via Reg 0x32[1:0].

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