TI E2E support forums
TI E2E support forums
  • User
  • Site
  • Search
  • User
  • E2E™ design support >
  • Forums
    • Amplifiers
    • API solutions
    • Audio
    • Clock & timing
    • Data converters
    • DLP® products
    • Interface
    • Isolation
    • Logic
    • Microcontrollers
    • Motor drivers
    • Power management
    • Processors
    • RF & microwave
    • Sensors
    • Site support
    • Switches & multiplexers
    • Tools
    • Wireless connectivity
    • Archived forums
    • Archived groups
  • Technical articles
  • TI training
    • Tech days
    • Online training
    • Live events
    • Power Supply Design Seminar
  • Getting started
  • 简体中文
  • More
  • Cancel
Interface

Interface

Interface forum

  • Mentions
  • Tags
  • More
  • Cancel
  • Ask a new question
  • Ask a new question
  • Cancel
Texas Instruments (TI) Interface support forum is an extensive online knowledge base where millions of technical questions and solutions are available 24/7. You can search interface IC content or ask technical support questions on everything from ESD protection to interfacing with USB, Ethernet, and HDMI. Find the right solution for your circuit design challenges by using our TI E2E™ support forums that are supported by thousands of contributing TI experts.
Frequent questions
  • [FAQ] How can I ensure a successful PCIe Gen5 design?

    Nicholaus_Malone
    Nicholaus_Malone
    3 Tips for a successful PCIe Gen5 design With PCIe datarates increasing to 32Gbps in the latest PCIe Gen5 specification, PCIe has allowed for data higher throughput than ever before. Unfortunately, higher data rates can also mean more signal integrity…
    • Answered
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] DP83867CR: How to generate free-running 125MHz clock from DP83867?

    Vikram Sharma
    Vikram Sharma
    Part Number: DP83867CR To generate free running clock of 125MHz on the CLKOUT pin of DP83867 (synced with local reference clock on XI pin) : program register 0x0170[12:8] = 01000
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] DP83867CR: How to generate recovered clock using DP83867?

    Vikram Sharma
    Vikram Sharma
    Part Number: DP83867CR To generate clock in sync with the link-partner (recovered clock of 125MHz or 25MHz) on the CLKOUT pin of DP83867 : program register 0x0170[12:8] = 00000 for 125MHz program register 0x0170[12:8] = 00100 for 25MHz Note…
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] ESD and TVS Protection Devices: All Technical Documentation

    Chris Murphy
    Chris Murphy
    Application Notes Protecting Automotive Can Bus Systems from ESD Overvoltage Events ESD and Surge Protection for USB Interfaces Automotive SerDes ESD Protection MSP430 System-Level ESD Considerations (Rev. B)…
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] DP83TD510E: Can we use a transformer instead of Capacitor for AC coupling on the MDI side for DP83TD510?

    Hillman Lin
    Hillman Lin
    Part Number: DP83TD510E Yes, transformer can be used for filtering out the DC signal when the data is passing through the MDI side. In fact, we use transformer to filter out the AC signal in the Power over Data Line (PoDL) application. Here are the…
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] What is the difference between RMII slave signaling and RMII master signaling?

    Hillman Lin
    Hillman Lin
    RMII slave signaling is connecting 50MHz Crystal to two XI pin of the PHY and/or MAC RMII master signaling is connection 25MHz Crystal to one Master and provide a 50MHz reference lock through REF_CLK pin to the XI pin of the slave side. Slave side does…
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] DP83TC812R-Q1: How can I connect PHYs back to back over RMII?

    Hillman Lin
    Hillman Lin
    Part Number: DP83TC812R-Q1 There are two type of mode that RMII can support: RMII normal mode and RMII Repeater mode: RMII normal mode is also known as MAC to PHY RMII connection. This mode is set as default mode in DP83TC812 so it did not need…
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] DP83TC811S-Q1: Why is Slave/Managed mode PHY linking up with Master/Autonomous PHY link partner?

    Gerome Cacho
    Gerome Cacho
    Part Number: DP83TC811S-Q1 Other Parts Discussed in Thread: DP83TC811R-Q1 When using DP83TC811S-Q1 (or DP83TC811R-Q1), and setting the PHY into managed mode as a slave device via bootstrapping settings, if this device is connected to a master link partner…
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] DS90UH949-Q1: Disable HDCP to work with UB Deserializer

    Alex Reid1
    Alex Reid1
    Part Number: DS90UH949-Q1 Hello, My customer would like to use DS90 UH949 -Q1 devices in place of the DS90 UB949A -Q1 to keep production running. In reviewing the details they have the following questions. Can the HDCP function be disabled? If…
    • Answered
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] Why am I getting "clause-45 not supported" and "error-95" errors with PHY drivers?

    Vikram Sharma
    Vikram Sharma
    Possible reason can be : - "phy_read_mmd" and "phy_write_mmd" are not supported in your kernel version (if version is old). Possible solution to be evaluated : - Change "phy_write_mmd" to "phy_write_mmd_indirect" function and do the corresponding…
    • over 4 years ago
    • Interface
    • Interface forum
<>

View FAQ threads
  • Tags
  • RSS
  • More
  • Cancel
  • Answered

    TIOL111: Current flow different between TIOL111 and TIOL1113. 0 Locked

    615 views
    5 replies
    Latest over 2 years ago
    by Kengo.Y
  • Answered

    DS90UB953A-Q1: Why is the FPD-Link III signal affected by smartphone signals, Wi-Fi signals? 0 Locked

    1443 views
    17 replies
    Latest over 2 years ago
    by Thomas Bejin
  • Suggested Answer

    DS90UB935-Q1: Minimum bypass capacitance 0 Locked

    403 views
    3 replies
    Latest over 2 years ago
    by Zoe Bison
  • Answered

    TLIN2029-Q1: Failure Modes and distribution 0 Locked

    466 views
    3 replies
    Latest over 2 years ago
    by Eric Hackett
  • Not Answered

    DS90UB954-Q1: data rate compatibilty and ser compatibilty with 971 0 Locked

    551 views
    5 replies
    Latest over 2 years ago
    by Thomas Bejin
  • Not Answered

    DP83826E: Difference between DP83826E and DP83826i 0 Locked

    777 views
    6 replies
    Latest over 2 years ago
    by Alvaro (Al-vuh-roe) Reyes
  • Suggested Answer

    DS250DF410: Application issues of chips 0 Locked

    330 views
    2 replies
    Latest over 2 years ago
    by Drew Miller1
  • Answered

    TFP410: replacement for Sil164CTG64 0 Locked

    630 views
    2 replies
    Latest over 2 years ago
    by Vishesh Pithadiya
  • Answered

    TPD3S716-Q1: what is status of VUBS_SYS and VIN when TPD3S716-Q1 is not powered and enabled and only VBUS_CON is powered by host PC 0 Locked

    666 views
    9 replies
    Latest over 2 years ago
    by Seong Kim
  • Answered

    DS08MB200: Propagation delay 0 Locked

    495 views
    1 reply
    Latest over 2 years ago
    by Amy
  • Suggested Answer

    LMH0397: output error 0 Locked

    307 views
    1 reply
    Latest over 2 years ago
    by Nasser Mohammadi
  • Discussion

    TUSB1142: Specification and ACTIVE cables Locked

    578 views
    6 replies
    Latest over 2 years ago
    by David (ASIC) Liu
  • Answered

    DP83822I: VDDIO and VAVD ramp sequence 0 Locked

    415 views
    2 replies
    Latest over 2 years ago
    by Dean Hofstetter
  • Suggested Answer

    DS80PCI102: DS80PCI102 design question 0 Locked

    369 views
    1 reply
    Latest over 2 years ago
    by Nasser Mohammadi
  • Suggested Answer

    DS160PR810: Using fiber optic to transmit PCIE signals 0 Locked

    601 views
    1 reply
    Latest over 2 years ago
    by Nasser Mohammadi
  • Answered

    TUSB2036: Review shcmatic 0 Locked

    531 views
    6 replies
    Latest over 2 years ago
    by Brian Zhou
  • Suggested Answer

    TCAN1462-Q1: ISO11898-2:2016 table14 spec? 0 Locked

    454 views
    1 reply
    Latest over 2 years ago
    by Eric Schott1
  • Suggested Answer

    DS25BR100: 4-channel LVDS signal with Cat5e cable 0 Locked

    664 views
    3 replies
    Latest over 2 years ago
    by Nasser Mohammadi
  • Answered

    DS90UB936-Q1: data rate compatibilty 0 Locked

    698 views
    7 replies
    Latest over 2 years ago
    by Darrah Merillat
  • Suggested Answer

    TDP1204: For DP1.4 0 Locked

    825 views
    7 replies
    Latest over 2 years ago
    by David (ASIC) Liu
<>