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Frequent questions

  • [FAQ] DP83TC811S-Q1: Why is Slave/Managed mode PHY linking up with Master/Autonomous PHY link partner?

    Part Number: DP83TC811S-Q1 Other Parts Discussed in Thread: DP83TC811R-Q1 When using DP83TC811S-Q1 (or DP83TC811R-Q1), and setting the PHY into managed mode as a slave device via bootstrapping settings, if this device is connected to a master link partner…

  • [FAQ] DS90UH949-Q1: Disable HDCP to work with UB Deserializer

    Part Number: DS90UH949-Q1 Hello, My customer would like to use DS90 UH949 -Q1 devices in place of the DS90 UB949A -Q1 to keep production running. In reviewing the details they have the following questions. Can the HDCP function be disabled? If…

  • [FAQ] Why am I getting "clause-45 not supported" and "error-95" errors with PHY drivers?

    Possible reason can be : - "phy_read_mmd" and "phy_write_mmd" are not supported in your kernel version (if version is old). Possible solution to be evaluated : - Change "phy_write_mmd" to "phy_write_mmd_indirect" function and do the corresponding…

  • [FAQ] DS90UB960-Q1: BIST Duration

    Part Number: DS90UB960-Q1 Hi Team, What is the recommended duration to run the BIST? Thanks Reed

  • [FAQ] How to select correct RGMII delay mode for PHY and MAC?

    RGMII standard asks for the introduction of delay in the clock (RX_CLK/TX_CLK) with respect to the respective data (RX_D*/RX_CTRL or TX_D*/TX_CTRL). This delay can be introduced at the source of the clock or at the receiver side. Following table should…

  • [FAQ] How to select the crystal's ppm specification for an Ethernet system?

    Other Parts Discussed in Thread: DP83TC811 Ethernet data travels effectively from one MAC to another MAC with two Ethernet PHYs in between. Each of these 4 ICs can have their own reference clocks and crystal attached to each is the usual source of this…

  • [FAQ] DP83867IR: DP83867 digital loopback fail, how to set MII and PCS loopback

    Part Number: DP83867IR Hi Team: Customer side need our help to find the root cause of DP83867 Communication failure issue from one failed board . could you please help to take a look at the attached , customer need to know How to enable MII and PCS…

  • [FAQ] RGMII Timing - Align and Shift mode

    Definitions: TX_DATA[3:0], TX_CLK (naming of TI Ethernet PHYs) are transmitted by the MAC/(Repeater PHY) and RX_DATA[3:0], RX_CLK (naming of TI Ethernet PHYs) are transmitted by Ethernet PHY. S.No Mode Definition 1 PHY: RX Align…

  • [FAQ] DS90UB933-Q1: DS90UB933-Q1 and DS90UB913A-Q1 MODE Decode

    Part Number: DS90UB933-Q1 Other Parts Discussed in Thread: DS90UB913A-Q1 , How do I determine if the DS90UB933-Q1 or DS90UB913A-Q1 device is operating in RAW10, RAW12LF, or RAW12HF through registers?

  • [FAQ] Demystifying Surge Protection

    Please refer to the links below to access our content related to Demystifying Surge Protection: Videos https://training.ti.com/getting-started-interface-protection White paper https://www.ti.com/lit/pdf/slyy152

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