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Frequent questions

  • [FAQ] Extended Register Space Access for Ethernet PHYs

    Our Ethernet PHYs have a standard set of registers, 0x0-0x1F, that can be accessed in a straight forward fashion. Registers beyond 0x1F require a different approach to access. This FAQ is intended to provide a few examples on how to read/write these…

  • [FAQ] SN65DSI86: SN65DSI86 Resolution Guide

    Part Number: SN65DSI86 What display resolution will the SN65DSI86 support?

  • [FAQ] DP83867E: What is the default mode of RGMII when using DP83867, shift or align?

    Part Number: DP83867E When bootstrapped to be in RGMII mode, DP83867 will be in shift mode by default; not align mode. The modes will be corroborated via Reg 0x32[1:0].

  • [FAQ] DP83869HM: How to generate 125MHz on CLKOUT pin for DP83869

    Part Number: DP83869HM DP83869HM needs an additional register to be written to enable CLKOUT modification. By default, this signal is a buffered version of the XI signal. Reg 0xC6 must have 0x10 written in order for the value in Reg 0x170[12:8] to take…

  • [FAQ] TI Ethernet PHY Capacitive Coupling (Transformerless Operation)

    Other Parts Discussed in Thread: DP83869 Summary: All of our Industrial Ethernet PHYs support Transformer-less Operation via Capacitive Coupling except for the DP83867. The DP83867 does not support Transformer-less Operation. List of Industrial…

  • [FAQ] DP83867E: Ethernet PHY SGMII Vdiff Upper and Lower Input Limits

    Part Number: DP83867E Other Parts Discussed in Thread: DP83869 The DP83867 and DP83869 both have the same Vdiff Upper and Lower Input Limits of: 100 mV and 800 mV

  • [FAQ] What capacitance should my ESD diode be?

    Other Parts Discussed in Thread: ESD2CANXL24-Q1 , ESD2CAN24-Q1 , ESD2CANFD24-Q1 , ESD122 What should be considered when selecting a diode with parasitic capacitance?

  • [FAQ] DP83825I: How to adjust the Output Differential Voltage (VOD) of the DP83825I

    4540.DP83825I VOD Adjustment.pptx

  • [FAQ] DP83TG720R-Q1: Why is my SGMII eye measurement distorted?

    Part Number: DP83TG720R-Q1 SGMII signal is high frequency low-voltage differential signal. Both layout design and measurements need to be accurate for good eye diagram capture. Common board design guidelines: 100ohms+/-10% differential traces…

  • [FAQ] Can an ESD diode experience latch-up?

    Other Parts Discussed in Thread: STRIKE Is there a risk of latch-up with ESD diodes? Should this be taken into design consideration?

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