Hi Board designers, 

1. Supported Interfaces 

PCIe 1x Single Lane Gen 2

1x USB 3.1 DRD

USB SuperSpeed and PCIe share a common SerDes PHY. Therefore, USB will be limited to non-SuperSpeed modes when using the
SerDes PHY for PCIe.

2. Implementation Reference for PCIe

Refer TMDS64EVM, AM64x evaluation module for Sitara processors

https://www.ti.com/tool/TMDS64EVM

3.  Implementation Reference for USB3.0

SK-AM64B, AM64B starter kit for AM64x Sitara processors

https://www.ti.com/tool/SK-AM64B

4. Can i use PCIe and USB3.0 interface at the same time 

The use of USB3.0 and PCIe interface are mutually exclusive (USB3.0 or PCIe). USB3.0 and PCIe
cannot be used at the same time.

5. Is AM64 able to change PCIE driving? If yes, how to do?

There is no support for PCIe swing tuning.

6. I see the clock generator used in the AM64x EVM mentioned as NRND. Any thoughts ?

Refer below E2E thread 

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1313243/faq-cdce6214-schematic-review---clock-generation-for-am644x

Regards,

Sreenivasa

Hi Board designers, 

SERDES0 inputs are not fail-safe.
If clock or data inputs are available before the SOC supply ramps, VDDR_CORE rail could be affected causing booting issues based on the power architecture implementation.

Refer below E2E.

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1335633/tps65219-without-output-it-is-only-outputting-three-times/5092501#5092501

Regards,

Sreenivasa

Hi Board designers, 

Note on Errata i2326

My customer is inputting non-SSC refclk from external source.

Is there any way they can find out if this errata does not apply to them?

Refer below E2E 

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1356536/am6442-errata-i2326-is-applied-in-the-use-case-of-separate-clock-architecture-also/5173823#5173823

Regards,

Sreenivasa 

Hi Board designers, 

Additional inputs regarding USB3.0

For configuring SERDES0 for USB3.0 interface as a host, refer SK-AM64B, PROC100A

https://www.ti.com/tool/SK-AM64B

USB3 interface configuration 

Can an A53 core-controlled USB interface be only a USB 3.0 host, not a USB 3.0 device at the 5Gbps rate?

USB3.0 in device mode is not support, only USB2.0 in device mode is support.

Refer TRM section 

USB chapter - table 12-2531

(35) AM6442: Checked the AM64X TRM - can an A53 core controlled USB interface be only a USB 3.0 host, not a USB 3.0 device at the 5Gbps rate? - Processors forum - Processors - TI E2E support forums

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1325476/am6412-pcie-link-down-issue/5072912

Regards,

Sreenivasa

Hi Board designers,

Refer below inputs regarding SERDES0 use case - contd.. 

AM6442: AM64 PCIe REFCLK

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1208861/am6442-am64-pcie-refclk

My comments below are based on the understanding that you're using the PCIe connector in both modes (socket for RC, edge for EP) and want to support generic add-in cards in RC mode. I mention this because the clocking requirements may change if you are using PCIe as a backplane bus on a single board solution.

In case of ROOT COMPLEX mode, we need to add 2 x 49.9ohm pull down resistor close to REFCLK balls of AM64.

Yes. The PCIe Card Electromechanical spec requires than any required REFCLK terminations be placed on the system board.

In case of ENDPOINT mode, these resistors must be removed.

Yes. Technically REFCLK terminations are not *prohibited* on an add-in card, but (paraphrasing from the same spec on this topic) "the same measurement techniques can be used as specified in that section, (double) receiver termination will reduce the nominal swing and rise and fall times by half. The low input swing and low slew rates need to be validated against the clock receiver requirements as they can cause excessive jitter in some clock input buffer designs.". TI doesn't characterize such a double-terminated REFCLK so we cannot support it.

Futhermore, is there any need to add serial resistor into REFCLK path?

Yes, these are recommended to reduce debouncing. Some tuning of the specific value may be needed for a specific board design, but we use 33 Ohm (R652/R653) and find it to be sufficient for most implementations.

AM6442: Serdes input clock (SERDES0_REFCLK)
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1364387/am6442-serdes-input-clock-serdes0_refclk

Q1: Yes, the EVM is operating in HCSL mode. HCSL clocking is required when operating in clock-input mode.
Q2: Yes, this SoC can source the 100MHz PCIe bus clock. Please note that this only applies to PG2.0. Refer to the silicon errata for more details.
Q3: This table is SerDes specific It means that the SerDes itself can operate as-described when provided any one of clock frequencies, but in the case of AM64xx, the only supported frequencies are 25MHz (internally clocked) and 100MHz (externally clocked).

(+) AM6411: 50 Ohm termination on PCIE refclk pin would affect biasing voltage? - Processors forum - Processors - TI E2E support forums

This board was designed to support multiple interfaces and clock-sources so the "biasing" vs "no-biasing" note isn't applicable to the GPEVM in its current state. The need for the 49.9 Ohm resistors depends on on the clock source you choose for your design. In the case of the GPEVM, they are required to produce a HCSL compliant signal.

More details can be found here: e2e.ti.com/.../am6442-am64-pcie-refclk

PCIe reference clock termination
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1178906/tda4vm-pcie-reference-clock-termination

TDA4VM reference clock pins as outputs, so does TDA4VM clock driver require the 50ohm termination? (HCSL compatible differential input is expected at receiver)

Yes, each signal should have 50-ohm resistor to GND near the source (TDA4VM).

(+) AM6422: Distorted Reference Clock on Serdes Refclock Input - Processors forum - Processors - TI E2E support forums

(+) AM6442: What is meaning of re-biasing in AM64 evm schematic? - Processors forum - Processors - TI E2E support forums

The EVM was designed to support multiple SERDES clocking configurations, hence the need for different BOM stuff options.

SERDES0 REFCLKP/N requires HCSL-level inputs when operating in input mode.

In the default (shipped) state, PCIe REFCLK is supplied to both the SoC and the PCIe connector via the CDCI6214 clock generator device operating in HCSL mode. For TMDS64GPEVM Revision PROC101B(001) you will find the required on-board 49.9 (1%) Ohm termination resistors for same installed as R681/R682 and R683/R684 respectively.

Applicability of LP-HCSL
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1385903/am5746-applicability-of-lp-hcsl

LP-HCSL is OK as long as it meets the PCIe Refclk specifications. Also, unlike HCSL, LP-HCSL integrates the termination resistors into the buffer so that they are not required to be placed on the PCB.

(+) TDA4AH-Q1: Is Low Power HCSL (LP-HCSL) okay for the SerDes REFCLK inputs? - Processors forum - Processors - TI E2E support forums

LP-HCSL and HCSL are mostly same for voltage levels, just termination/power levels are different.  We have not tested, but think it should work without issue.

(+) TDA4VH-Q1: PCIe signal and connector impedance - Processors forum - Processors - TI E2E support forums

The TDA4VH's REFCLK input type is HCSL. Yes - LPHCSL driver should be compatible with TDA's clock receiver.

(+) DRA821U: SERDES REFCLOCK (PCIe) Reference Clock Input Characteristics - Processors forum - Processors - TI E2E support forums

What about series DC blocking capacitors, as mentioned in the referenced E2E thread above? Should these still be used?

No, neither HSCL nor LP-HSCL use DC blocking caps. Those would only be necessary if rebiasing the common mode, for example when trying to interface an LVDS output with an HSCL-compliant input

SERDES REFCLK & PCIE CLK HARDWARE DESIGN
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1376467/tda4vh-q1-serdes-refclk-pcie-clk-hardware-design/

LPHCSL output can be used to drive a HCSL input. The LP-HCSL spec was developed to be signal level compatible with HCSL so that the RX side doesn’t know the difference.
It is recommended to drive 1:1, one LPHCSL output to one HCSL receiver. close this thread.

TDA4 serdes REFCLK
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1062475/tda4vm-tda4-serdes-refclk

SERDES0_REFCLK Termination when used as Input
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1073497/dra821u-serdes0_refclk-termination-when-used-as-input

SERDES REFCLOCK (PCIe) Reference Clock Input Characteristics
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1082419/dra821u-serdes-refclock-pcie-reference-clock-input-characteristics

AC coupling and biasing
https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1110905/cdci6214-ac-coupling-and-biasing

PCIe reference clock termination
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1178906/tda4vm-pcie-reference-clock-termination

Heterogenous multiprocessor design - clock generator synchronisation
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1301716/tda4ve-q1-heterogenous-multiprocessor-design---clock-generator-synchronisation/

Rising/falling time failed for HCSL output
https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1191081/lmk03318-lmk03318---rising-falling-time-failed-for-hcsl-output

CDCI6214RGE vs CDCE6214RGE: What are the differences?
https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1409617/cdci6214-cdci6214rge-vs-cdce6214rge-what-are-the-differences/

LP-HCSL vs HCSL
https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1015683/cdce6214-lp-hcsl-vs-hcsl

From output level perspective, there's no difference. LP (Low Power)-HCSL, by its name, is more power saving. Also, there's internal 50Ohm termination for LP-HCSL so no need for external termination. Traditional HCSL may or may not have internal 50Ohm.

Common mode voltage of HCSL output
https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1302140/cdce6214-q1-common-mode-voltage-of-hcsl-output/

LP-HCSL is typically defined in terms of min and max swing and a single-ended crossing voltage (in place of a common mode voltage), per the PCIe specification. This single-ended crossing point voltage is between 250 mV and 550 mV.

Termination for HCSL output to input of LMK00725
https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1118844/lmk00725-termination-for-hcsl-output-to-input-of-lmk00725

HCSL Output pin state when disabled
https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1373376/lmk5b33216-hcsl-output-pin-state-when-disabled

Can I use HCSL signal as clock input?
https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1353002/adc3562-can-i-use-hcsl-signal-as-clock-input/

800mV is single-ended so is 800mVp (peak). Differential of that is 1.6Vpp (peak-to-peak) so it will work.

App Note SLAAE45 – SEPTEMBER 2021, Table 2-1 PCIe Requirements
https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1399454/tmuxhs4412-question-about-ti-app-note-slaae45-september-2021-table-2-1-pcie-requirements/

AM6442: AM6442 PCIE Driver in RC mode

e2e.ti.com/.../am6442-am6442-pcie-driver-in-rc-mode

[FAQ] AM6442: PCIe clock architecture

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1421351/faq-am6442-pcie-clock-architecture

AM6442: PCIe Clock Review for AM6442

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/999445/am6442-pcie-clock-review-for-am6442/4775833

AM6412: SERDES0_REFCLK selection

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1421341/am6412-serdes0_refclk-selection

AM6442: How to configure SERDES0_REFCLK as an output and route internal PCIe reference clock to them?

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1332399/am6442-how-to-configure-serdes0_refclk-as-an-output-and-route-internal-pcie-reference-clock-to-them

AM6442: Generating PCIe Clock from AM6442

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1503363/am6442-generating-pcie-clock-from-am6442

AM6442: PCIe external reference clock

e2e.ti.com/.../am6442-pcie-external-reference-clock

AM6442: PCIe REFCLK input in root complex mode

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1487077/am6442-pcie-refclk-input-in-root-complex-mode

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1415321/tda4vh-q1-serdes-refclk-hcsl-output

TDA device is the source for the PCIe clock?  Assuming yes - the 50-ohm resistors need to be included externally (added to your PCB design) and should be place relatively close to TDA pins

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1490944/am6412-if-pcie-refclk-support-lp-hcsl

if a clock driver is necessary for you then it should be HCSL.   I want to point out that AM6412 silicon Rev2 will support sourcing PCIe refclk

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1524458/am6442-2-x-tmds64evm-pcie-connected-back-to-back-1-as-ep-1-as-rc

REFCLK is not propagated, so I suppose than synchronization is done by using Independent Reclks (IR) and not Common Refclk (CC)

I only ever used the MCU+ SDK AM64x + AM64x examples, and they work just fine with independent Refclk. One one x86 system we were having problems unless we were using a common reference clock (which is mandated by the PCI express card standard).

you don't propagate the +3.3V neither +12V from root complex to end point, so the 2 boards are powered externally to the PCIe connector.

it's mandatatory to have end point ready to be enumerated before the host is ready to enumerate because the host have a timeout shorter than time for the endpoint to boot.

The PCIe specifications (PCIe itself and the electromechanical specification for the PCI express card, i.e. what you'd commonly call a PCIe card) specify that the EP can expect at least 100ms of stable power before PERST is released, and then EP has 20ms until it should be able to enter link training. Since an AM64x can't boot within that time, especially not when running Linux, you need the EP up and running before the RC.

The MCU+ SDK documentation for the pcie_enumerate_ep example (currently the example Linux RC driver is NOT compatible with an AM64x as an RC) has more details: https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/11_00_00_15/exports/docs/api_guide_am64x/EXAMPLES_DRIVERS_PCIE_ENUMERATE_EP.html

You don't want PORz for timing reasons and obviously you don't want to connect one output to another output. 

On the AM64x there is no hardware switch for that. There are jumpers J34 (PERST) and J35 (PRNST). PERST I explained above, and PRNST you can ignore for AM64x EVM <-> AM64x EVM.

For Linux the device tree configures RC vs. EP. For MCU+ SDK it merely depends on the software you run.

(+) LMK00301: Do I need to add a matching circuit when the clock signal input is LP-HCSL - Clock & timing forum - Clock & timing - TI E2E support forums

(+) LMK1D1204: LP-HCSL / HCSL input termination - Clock & timing forum - Clock & timing - TI E2E support forums

(+) TDA4VH-Q1: SERDES Refclk HCSL Output - Processors forum - Processors - TI E2E support forums

TDA device is the source for the PCIe clock?  Assuming yes - the 50-ohm resistors need to be included externally (added to your PCB design) and should be place relatively close to TDA pins.

You do NOT have to include the 33-ohm series resistors on the board.

(+) TDA4VH-Q1: PCIe refclk output, termination resistor placement - Processors forum - Processors - TI E2E support forums

The PCIe_REFCLK driver IO is similar to HCSL and requires 50-ohms to GND near the source.  To confirm - you have 50-ohm resistor to GND on each P and N clock signal?  Also you routed in such a way not to create stub nets (route the trace through the resistor pad and not to the resistor pad?

(+) DRA829V: PCIE_REFCLK distortion - Processors forum - Processors - TI E2E support forums

To use an external Refclk, ensure that the Refclk IOs of the Serdes are set to Input mode, and that only one set of termination is present (either external termination on the PCB or internal termination turned on in the Serdes). Also ensure that the external clock generator is configured in HSCL output mode

(+) DRA821U: PCIe termination resistors and SI - Processors forum - Processors - TI E2E support forums

DRA821 supports PCIe-standard link autonomous equalization upon training to 8.0GT/s speed. This is an automatic negotiation between link partners to adjust the Transmitter and the Receiver setup of each Lane to improve the signal quality. Software can optionally set Preset Hints per the PCIe standard if desired, based on their system requirements.

(+) AM5728: PCIe external clock SI issues - Processors forum - Processors - TI E2E support forums

(+) [DRA829] PCIe ref clock AC-coupling capacitor - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa

Hi Board designers,

Notes regarding setting the PCIe configuration

(44) [FAQ] AM6422: How to configure the PCIe align with the simulation results.? - Processors forum - Processors - TI E2E support forums

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1462622/faq-am6422-how-to-configure-the-pcie-align-with-the-simulation-results

Regards,

Sreenivasa

Hi Board designers,

Refer below inputs regarding supported speed:

Question:

There is a reference to SERDES_10G0 in the SDK and the TRM. Customer is asking for additional information or assuming the serdes support 10G. Can you please provide your thoughts on the SERDES_10G0.

AM64x only supports USB3.1 SuperSpeed Gen1 (5Gbps) or a single lane of PCIe Gen2 at 5GT/s. Refer above replies (quoted below) for information on the supported interface configuration. Refer processor-specific data sheet for the supported speeds. 

Kallikuppa Sreenivasa said:

dditional inputs regarding USB3.0

For configuring SERDES0 for USB3.0 interface as a host, refer SK-AM64B, PROC100A

https://www.ti.com/tool/SK-AM64B

USB3 interface configuration 

Can an A53 core-controlled USB interface be only a USB 3.0 host, not a USB 3.0 device at the 5Gbps rate?

USB3.0 in device mode is not support, only USB2.0 in device mode is support.

Refer TRM section 

USB chapter - table 12-2531

(35) AM6442: Checked the AM64X TRM - can an A53 core controlled USB interface be only a USB 3.0 host, not a USB 3.0 device at the 5Gbps rate? - Processors forum - Processors - TI E2E support forums

In the SDK and TRM SERDES_10G0 is just the name of the multiprotocol serdes (IP), It does not mean the chip supports 10Gbit/s speed on PCIe or USB in the instantiation on AM64x. 

So, some memory area are reserved for "SORDES10G0" according to TRM.

.

Where can I see the register description for that?

The details for the SERDES are in section 12.2.3.1 SerDes Overview of the TRM. We do not support arbitrary configuration of the SERDES registers by customers. It is only supported in PCIe and USB drivers using code from TI.

Regards,

Sreenivasa

HI Board designers,

Inputs related to PCIe REFCLK

We pulled up the MCU+SDK to determine what could be done, and if the customer is using MCU+SDK as code base, it seems like customer would need to just define in ti_drivers_config.c   “.refclk_mode = PCIE_REFCLK_MODE_INT_NOSSC_OUTEN” as that would set needed flags to enable.

Linux

Is customer is using Linux as I believe the SDK will by default source RefClk out to pins from being generated our SOC’s PCIe internal clock.

there are at least a couple registers which are related to control the refclk direction. Linux user only need to modify kernel devicetree for the refclk direction.

Note from expert:

I don’t believe the register for Phy_en_refclk is available in the TRM

below FAQs could be used as reference:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1503363/am6442-generating-pcie-clock-from-am6442

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1421341/am6412-serdes0_refclk-selection

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1332399/am6442-how-to-configure-serdes0_refclk-as-an-output-and-route-internal-pcie-reference-clock-to-them

Regards,

Sreenivasa

HI Board designers,

Refer below FAQ for general description for the below question:

How do I check to make sure my PCIe signals are AC-coupled correctly?

(+) [FAQ] DS320PR810: How should PCIe signals be AC coupled? - Interface forum - Interface - TI E2E support forums

PCIe is fundamentally an AC-coupled signal type. This means that a capacitor is placed in series with a PCIe signal line to attenuate the low frequency content of the signal while allowing the higher frequency content to pass through. In general, the main purpose of AC coupling on high speed signals is to remove the DC component of the transmitted signal so that the receiver can re-bias it to its preferred level, but there are other functions and benefits as well. For PCIe Gen 4 and Gen 5, the typical and recommended AC coupling capacitor size is 0.22 μF (i.e. 220 nF).

Although redrivers are simple ICs that can operate "transparently" in the PCIe link between the root complex and endpoint, because redrivers are still active devices with amplifiers, they do split the direct electrical connections between the root complex and endpoint into indirect electric connections that pass through the redriver. So we should pay attention to the treatment of AC coupling in redriver projects. 

Each PCIe line should be AC-coupled exactly one time, and it's important to double check this during the schematic and layout design phases of a project using PCIe redrivers:

• If AC capacitors are forgotten and a data line is accidentally not AC-coupled at all, there could be major signal quality issues
  • Mismatches can happen when the receiver tries to work on a signal that already has a nonzero DC component, particularly if the internal voltages of the transmitter and receiver are not the same
  • We have seen that the signal quality issues can prevent any PCIe data from being successfully understood at all, resulting in no link up.
    • This is an especially difficult problem to deal with when discovered during board testing because it is hard or impossible to add capacitors onto data lines that have no pads for them. So a new board revision would be required before anything else about the signal paths (such as generic SI problems) can be tested and corrected.
• It is better to avoid accidentally AC-coupling a data line two times
  • If two identical AC coupling capacitors are in series, their combined capacitance is half of the individual value.
  • The combined value might be outside of the allowable capacitance range in the PCIe specification. Even if it is not, it would lead to some changes in the frequency content of the signal.
  • Although double coupling is not as likely to cause significant problems as no coupling, there is still no benefit, and when working with signal conditioning devices it is preferrable to keep the electrical conditions as consistent and simple as possible.

Regards,

Sreenivasa

Hi Board designers, 

Inputs related to Trace requirement for PCIe reference clock and differential pairs

AM6442 can be either as USB3 or PCIe but not both.  

(+) TDA4VH-Q1: PCIe signal and connector impedance - Processors forum - Processors - TI E2E support forums

(+) TDA4VM: TDA4 serdes REFCLK - Processors forum - Processors - TI E2E support forums

(+) AM2434: Recommended Typ PCB single-ended impedance and differential impedance for DDR and PCIE - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

(+) AM6412: Query related to Differential impedance for PCIE interface Gen@2 - Processors forum - Processors - TI E2E support forums

The PCIe specification limit for GEN2 max differential impedance is 105 Ohms. TI cannot recommend exceeding this value.

AM6548: AM65x PCIe differential impedance control question

(+) AM6548: AM65x PCIe differential impedance control question - Processors forum - Processors - TI E2E support forums

The AM65x recommendations are an attempt to accommodate the use of USB3 and PCIe GEN3 on the same channel as is done on our EVM. However, the use of PCIe GEN3, which requires tighter impedance control, has since been deprecated by Device Erratum i2104.

If this customer is only using PCIe, and only in GEN1 and/or GEN2 mode(s), a target differential impedance of 100 Ohms (+/- 10%) for this channel can be supported. Please ensure that the resulting design is simulated prior to manufacturing as tighter impedance control may be required depending on board-specific variables such as channel length, PCB substrate material, connectors, link partner, vias, etc.

Skew within any USB3/PCIe differential pair needs to be considered.

www.ti.com/.../spraar7j.pdf

https://www.ti.com/lit/an/spracp4a/spracp4a.pdf

Please refer below recommendations on the length matching for clock and signal differential pairs. Please let customer know that the below recommendations are expected to be followed.

Reference 

PCI Express® Card Electromechanical Specification Revision 3.0

2.1.1. Low Voltage Swing, Differential Clocks

To reduce jitter and allow for future silicon fabrication process changes, low voltage swing, differential clocks are being used, as illustrated in Figure 2-1. The nominal single-ended swing for each clock is 0 to 0.7 V and a nominal frequency of 100 MHz ±300 PPM. The clock has a defined crossover voltage range and monotonic edges through the input threshold regions as specified in Chapter 4.The reference clock pair is routed point-to-point to each connector from the system board according to best-known clock routing rules. The reference clock distribution to all devices must be matched to within 15 inches on the system board. The transport delay delta between the data and clock at the Receiver is assumed to be less than 12 ns. The combination of the maximum reference clock mismatch and the maximum channel length will contribute approximately 9-10 ns and the remaining time is allocated to the difference in the insertion delays of the Tx and Rx devices. The routing of each signal in any given clock pair between the clock source and the connector must be well matched in length (< 0.005 inch) and appropriately spaced away from other non-clock signals to avoid excessive crosstalk.

 4.7.7. Skew within the Differential Pair

The skew within the differential pair gives rise to a common-mode signal component, which can, in turn, increase Electromagnetic Interference (EMI). The differential pair shall be routed such that the skew within differential pairs is less than 0.127 mm (5 mils) for the add-in card and 0.254 mm (10 mils) for the system board.

For AC coupling values refer to: PCI Express® Base Specification Revision 3.0

(+) AM67A: Trace requirement for PCIe reference clock - Processors forum - Processors - TI E2E support forums

Based on the below i suspect all differential pairs are expected to be matched. (the above appnote for Sitara processor also mentions all differential pairs)

https://www.ti.com/lit/an/slla295a/slla295a.pdf

(+) AM67A: PCIe reference clock - Processors forum - Processors - TI E2E support forums

1 - yes AM67A has several errata items related to PCIe and specifically clocks.  I can't say is necessary to use external clock - that is dependent on how you are using PCIe and if the errata items will impact you.  But certainly some of the work-arounds for the issue(s) involve using an external refclk. 

2 - No in-line capacitor is required.  LMK3H0102 can be connected directly to AM67 and PCIe connector/peripheral.

Additional Information (FYI only)

(+) [FAQ] DS80PCI102: How does PCIe Receiver Detection work? - Interface forum - Interface - TI E2E support forums

(+) [FAQ] DS80PCI102: PCIe RX Detect Pulse Timing - Interface forum - Interface - TI E2E support forums

(+) AM6412: PCIe link down issue - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivasa

Hi Board Designers,

LMK3H0102 Bulk acoustic wave (BAW)-based PCIe Gen 1 to Gen 7-compliant referenceless clock generator

(+) LMK3H0102: Does LMK3H0102 in LP-HCSL mode compatible with AM64 PCIe REFCLK input? - Clock & timing forum - Clock & timing - TI E2E support forums

Please refer below.

(8) AM6442: Serdes input clock (SERDES0_REFCLK) - Processors forum - Processors - TI E2E support forums

HCSL clocking is required when AM644x is operating in clock-input mode.

I understand LMK3H0102 can support LP-HCSL with internally selectable 85 Ohm or 100 Ohm termination for PCIe Gen 1 to PCIe Gen 7 compliance

Sandra Saba said:

For differences between the HCSL and LP-HCSL you can refer to this thread 

I understand from the above link the amplitudes are similar.

Based on the above any thoughts if the LMK3H0102 output connected to the AM644x is likely to work (agree this needs to be tested) or do you see some concerns that needs additional analysis. 

i dont see any concerns for the use of LMK3H0102, and there is no need populate the external termination resistors as you would for the HCSL format 

Regards,

Sreenivasa