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Clock & timing

Clock & timing

Clock & timing forum

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Texas Instruments (TI) Clock & timing support forum is an extensive online knowledge base where millions of technical questions and solutions are available 24/7. You can search clock & timing IC content or ask technical support questions on everything from clock synchronizers and generators to clock buffers and timers. Find the right solution for your circuit design challenges by using our TI E2E™ support forums that are supported by thousands of contributing TI experts.

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Frequent questions
  • [FAQ] TLC555: What are the performance differences expected for TLC555 PCN 20231130002.1?

    Ron Michallick
    Ron Michallick
    Part Number: TLC555 Other Parts Discussed in Thread: , TLC3555-Q1 , TLC3555 Tool/software: PCN 20231130002.1 is the “Qualification of RFAB using qualified Process Technology, Die Revision, Datasheet update and additional Assembly Site/BOM options…
    • Answered
    • 1 month ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] Does TI have crosses for obsolete Analog Devices HMC103x, HMC7xx, HMC8xx PLL family products and other discontinued products such as ADF5610 and HMC987 as per the Product Discontinuance Notice issued by ADI on March 22, 2022?

    Vibhu  Vanjari
    Vibhu Vanjari
    TI’s wide portfolio of RF PLLs & synthesizers features devices that are potential crosses for Analog Devices HMC103x, HMC7xx, HMC8xx PLL family products and other discontinued products such as ADF5610 and HMC987. With most of TI’s RF PLLs & synthesizers…
    • over 3 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] TPL5010: How to disable the watchdog function of TPL5010

    Dong Shen1
    Dong Shen1
    Part Number: TPL5010 Hi all, I am a FAE of TI,now my customer has a watchdog disabled problem, so I synchronously ask you for a solution: Problem Description: the customer's MCU wants to disable the watchdog function during the recording program…
    • Answered
    • over 3 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] Clock Buffers: How to connect the unused pins?

    Kia Rahbar
    Kia Rahbar
    When a pin on my clock buffer is not being used, what is the correct termination?
    • Answered
    • over 4 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] Clock Buffers: Can my buffer handle an input while it is powered off?

    Aaron Black
    Aaron Black
    If my buffer is powered off can an input go into the device without damaging it?
    • Answered
    • over 4 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] RF synthesizers: How to deal with the unused output differential pin in a RF synthesizer?

    Noel Fung
    Noel Fung
    I need single-ended output, how to deal with the unused output differential pin?
    • Answered
    • over 4 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] RF synthesizers: Sample programming code for RF synthesizers

    Noel Fung
    Noel Fung
    Can TI provide sample code to program RF synthesizers?
    • Answered
    • over 4 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] RF synthesizers: What is MASH order and how to determine the suitable MASH order in RF synthesizers?

    Noel Fung
    Noel Fung
    Can you tell me what is MASH order and how to determine the suitable MASH order?
    • Answered
    • over 4 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] RF synthesizers: What is PFD delay and how to determine the value?

    Noel Fung
    Noel Fung
    Can you tell me what is PFD delay and how to determine the value?
    • Answered
    • over 4 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] RF synthesizers: Where is the Dean's book?

    Noel Fung
    Noel Fung
    I cannot find and download Dean Banerjee's PLL Performance, Simulation, and Design book. Can you tell me where I can get a copy?
    • Answered
    • over 4 years ago
    • Clock & timing
    • Clock & timing forum
>

View FAQ threads
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  • Not Answered

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    1 reply
    Latest over 2 years ago
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    LMX2820: Can each pair of differential outputs of LMX2820 be used as two single-ended outputs? 0 Locked

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  • Suggested Answer

    Max Vdiff for LVPECL output & LVPECL Like to LVDS termination 0 Locked

    554 views
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    Latest over 2 years ago
    by Julian Hagedorn
  • Answered

    LMX2594: Regarding multiple programmable output channels 0 Locked

    324 views
    5 replies
    Latest over 2 years ago
    by Noel Fung
  • Suggested Answer

    LMK04828BEVM: Set frequency and actual frequency do not match 0 Locked

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    LMX2572EVM: LMX2572 0 Locked

    325 views
    1 reply
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    by Noel Fung
  • Suggested Answer

    TPL5010: Will any Nanotimer products be offered in smaller packages (SC70, BGA, UQFN) 0 Locked

    248 views
    1 reply
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    by Noel Fung
  • Suggested Answer

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    by Almog Hershko
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    464 views
    10 replies
    Latest over 2 years ago
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  • Suggested Answer

    LMX2571: Is there any guideline for configure R, N and num, den when use LMX2571&2572? 0 Locked

    431 views
    4 replies
    Latest over 2 years ago
    by Harry Ma
  • Not Answered

    LMK03318: Clock & timing forum 0 Locked

    466 views
    3 replies
    Latest over 2 years ago
    by vicente flores prado
  • Answered

    TICSPRO-SW: Exporting register values for LMK04828B does not match settings 0 Locked

    320 views
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    Latest over 2 years ago
    by Reid Crowe
  • Answered

    LMX2572EVM: MASH order 0 Locked

    533 views
    2 replies
    Latest over 2 years ago
    by David N Shelef
  • Answered

    LMX2820: PLL lock issue 0 Locked

    1209 views
    6 replies
    Latest over 2 years ago
    by Kiran Kumar R
  • Answered

    LMK04826: LMK04826 for JESD204C link can't establish if SYSREF divide from VCO 0 Locked

    438 views
    5 replies
    Latest over 2 years ago
    by Ajeet Pal
  • Answered

    LMX2820EVM: The mesured Phase Noise @10kHz~100kHz offset at Fpfd=100MHz does not match the simulated values 0 Locked

    692 views
    6 replies
    Latest over 2 years ago
    by Masashi Wada
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