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Frequent questions

  • [FAQ] DS125DF1610: How to setup DS125DF1610 cross point registers?

    Part Number: DS125DF1610 You have different trace lengths on inputs of the DS125DF1610 device. How do you set up cross point registers to allow every channel CTLE to adapt to it's incoming signal loss characteristics?

  • [FAQ] DS125DF111: How to determine the data rate that device is lock to?

    Part Number: DS125DF111 DS125DF111 is locked and you want to know what is the data rate that device is locked at. What are the settings to determine DS125DF111 locked rate?

  • [FAQ] LMH0303: How to setup LMH0303EVM to operate in Pin mode or use external SMBus controller?

    Part Number: LMH0303 Other Parts Discussed in Thread: LMH0318 , SIGCONARCHITECT , LMH0397 , , LMH0307 , USB2ANY LMH0303EVM/LMH0307EVM GUI was developed using win XP OS. Majority of PCs now run win10 and it is incompatible with LMH0303EVM GUI. How do we control…

  • [FAQ] DS280DF810: How to use SigconArchitect to program 16-bits User Defined Generator Pattern

    Part Number: DS280DF810 Other Parts Discussed in Thread: SIGCONARCHITECT There are two purposes for this FAQ: 1). Channel register settings - using FPGA or ASIC - to generate 16-bits user pattern used for mask compliance test or other purposes. 2). Use…

  • [FAQ] When implementing a USB 3.x signal redriver, what is the difference between pre-channel loss and post-channel loss?

    Other Parts Discussed in Thread: TUSB1002A I am implementing a USB 3.x signal redriver to help with signal integrity issues. I understand that a redriver provides equalization to the signal path but what losses are affected by this equalization?

  • [FAQ] How do I debug a TI USB Hubs when downstream ports are non-operational?

    Other Parts Discussed in Thread: TUSB8044 , TUSB8041A , TUSB8043 , TUSB8042 , TUSB4020BI , TUSB8020B , TUSB8041 , TUSB4041I I have implemented a USB Hub with four USB 3.1 Gen / USB 2.0 ports using TUSB8044 however the downstream ports don’t work when the hub…

  • [FAQ] How to Enable DSxxxDFxxx to Lock to Any Data Rate within VCO Range

    Part Number: DS280DF810 Other Parts Discussed in Thread: SIGCONARCHITECT In this example, we use a non-standard data rate - for example 24.33Gbps - and configure register settings to lock to this data rate. Note: Data rate MUST be within the device VCO…

  • [FAQ] DS280DF810: What are register settings to enable prbs generator and checker using a simple divide by 2, 4, or 8 clock

    Part Number: DS280DF810 Using DS280DFxxx or DS250DFxxx we can use a simple divide by 2, 4, or 8 of the data rate clock to generate different prbs pattern at different data rates up to 28Gbps. What are the register settings to make this happen?

  • [FAQ] DS250DF410: How to setup PRBS pattern generation/checker using divide by 2, 4, or 8 clock

    Part Number: DS250DF410 Other Parts Discussed in Thread: SIGCONARCHITECT Using a simple clock, DS250DFxxx and DS280DFxxx can generate different prbs patterns at different data rate up to 28Gbps. To make it very simple, SigconArchitect can be used to achieve…

  • [FAQ] PCA9306: Voltage levels translation

    Part Number: PCA9306 To allow proper translation of I2C signals from one voltage reference to another, both the high-level and low-level voltage thresholds need to be translated. However, these threshold voltages are not mentioned in the datasheet of…

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