Tool/software:

CDCE62005 Loop Filter Setting Inquiry.

I want to set the same as TMS320C6678 EVM Board, Product name: DSPM-8301E.

Currently, PLL Lock is unstable.
It seems to be a problem…

Hello,

The customer attempted to create the configuration below using the CDCE62005 GUI, but an error occurred.

   - AUX IN : 25MHz

   - Output 0 : 100MHz / Output 2 : 66.667MHz / Output 3 : 100MHz

Below is the error message.

Please…

Dear TI support,

Appreciate your answers to the following questions below:

1. Does CDCE62005 come pre-burned from TI with our specific specifications?

2. The clock generator need to be configured every power-up?

3. Is there an external…

Hi,

I need your expert advice.

The idea is to use this component as basic LVDS output OSC with 3 outputs 250, 50 and 100MHz

1. I can not use pins 43 (Auxin), SECREF(3,2), and PRIREF(45,46)…

hello, I want to initialize and program CDCE62005 with my own circuit. But now I have some problems.

First, I am not sure whether the peripheral circuit of the chip built is correct, I cannot confirm whether the chip works, and…

Hello,

I connect CDCE62005 to TI DSP TMS320C6655, but I using only 3 input clocks in this DSP, (Core, SGMII, and DDR) so I need only 3 LVDS outputs from CDCE62005.

Should I leave the unused…

Hi,

We meet a problem: we use two CDCE62005 multistage cascaded, some the 2nd chip's lock signal on the board is unlock.
Our SCH is the same as TI 6678 EVM, using SPI interface from FPGA, and the config file is created from TI…

Hello,

 Our customer used two CDCE62005 for cascade application. But some of the board the second CDCE62005 couldn't be lock.

His description is as following:

Our  circuit is fully referenced to TI's official 6678 development…

Hello team,

I have a quick question about CDCE62005.

Is there performance difference between when using PRI_REF and when using SEC_REF?

Best regards,

Hello team,

Could you let me know if there is any requirement on below pins during power up? for example, it needs to be pulled to GND, floating is fine, and so on.

•  AUX_IN
• PRI_REF+/-
• SEC_REF+/-
• SPI_CLK
• SPI_LE
• SPI_MOSI
• SPI_MISO

Hi Team!

My customer is interested in using DAC3171 to convert digitized ultrasound data to an analog output.

They want to use a 400MHz LVDS clock from FPGA to drive the DACCLK LVPECL…

Hello team,

VIN(VIN-V/IN) of Differential input mode is specified with 0.1V(min) and 1.3V(max).

Does this 0.1V mean 0.1Vpp which is from +/-0.025V swing around common voltage at pos side and -/+0.025V swing around common voltage…

Dear TI team,

I have A situation where I am outputting an LVDS Clock output from CDCE62005 to LTC2107IUK @ 200MHz.

But the LVDS lines are crossing each other on the PCB. I do not want much layer changes as I need a dual pair of VIAs…

I want to create a multiplying wave that changes following a reference signal with a fluctuating frequency.
I want to synchronize the reference signal at 1.7MHz and change it within the…

Hi,

Good Day. Customer is doing R&D on using NMR to build a non puncture phlebotomy process for blood work or blood chemical content and he must have specific frequencies for…

Hi team,

Do you have any loop filter calculation tool for CDCE62005?

I found CDCE62005EVM GUI has loop filter calculation tool, but can I use this tool without EVM?

or do you have any excel calculation tool on Loop filter?

I want to…

Hi,

This is Hemila from HCL Technologies working in Dhiviya' s team.

We are trying to write to EEPROM using CDCE62005 but we are not able to do it. We can write and read all SPI registers.

Is there any possibility to write EEPROM…

Hi

We have tried loading registers in CDCE62005 using Control software. The problem is we couldn't write in EEPROM. We have to load the register settings every time we power up.

What could be the possible reason for EEPROM write…

Dear Clock team,

I was advised to contact you again from Data Converters team as the following,

DAC34H84EVM: J10/J11 CDCE62005 LVDS clock output error.

Please review attached configuration…

Dear Team,

My customer evaluating the DAC34H84EVM with the DAC348x EVM Software GUI. They want to set LVDS clock output as 207.36MHz from J10/J11 pins of the DAC34H84EVM which are U4P/U4N pins of the CDCE62005. The DAC34H84EVM has…

Hi Ti Team

I have downloaded 

Hello,

Since we are starting a new design with the TMS320C6678, I understand that the CDCE62005 is a good choice to provide the LVDS clocking for the DSP: 100MHz for…