Tool/software:

Dear Technical Support Team,

I have been looking into the clock generator and jitter cleaner.

Input recovery clock from AMD FPGA SerDes…

Tool/software:

LMK04828: 
DCLK :144MHz 
SYNC PIN :9MHz Under the condition, sdclk(sysref) duty cycle is not 50%. 
In the sdclk(sysref) output port Some output ports satisfy 50%, but othersdclk(sysref) output ports are around 56…

Tool/software:

Hi Team,

I am using LMK04808 device.

Do we need to program LMK04808 for each power-on?

Can we program the LMK04808 one time and avoid programming it on each power…

Tool/software:

I am currently debugging the development board with 3 AD9695 (namely A, B, and C) and 1 lmk04828 clock chip. The lmk04828 chip operates in Cascaded Zero-Delay Dual-Loop Mode, and the sysref is continuously generated…

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We are working on ZCU208 board. We need to generate 1.96416GHz sampling rate with external clock 10.23MHz to CLK104 module consisting of LMK04828B.

I did configuration in TICs…

Tool/software:

Hi everyone,

I have a design similar to the ADC08DJ3200EVM with an ADC08DJ3200, a LMK0828 and a LMX2582. The design works on a lot of the boards…

Tool/software:

Hello,

I am using the CLK104 board from Xilinx which contains LMK04828B and LMX2594 PLLs to drive clocks int the ZCU208 eval board from Xilinx again. The CLK104 board also has…

Tool/software:

Hi,

As a follow up to our earlier query, when we use the ethernet recovered clock from another ZCU208 board for clkin2 input, PLL locks successfully.

However when we use the ethernet recovered clock from our custom…

Tool/software:

Hi expert,

My customer is evaluating LMK04828 and met a issue as below, please help to confirm. Thanks.

• The output of LMK04828 is normally locked when it power-on firstly. But the PLL2 would lost lock when R&D configure…

Tool/software:

Hi Team, 

I want to interface the LMK04828B Clock Generator, ADC12QJ1600AAVQ1: Analog to Digital Converter (ADC), and DAC37J84IAAV: Digital to Analog Converter (DAC) with the…

Tool/software:

I'm getting errors in TicsPro about the vco frequency and the calibration frequency not being equal for 0-delay mode

with the clkdiv for DClkOUT8 = 1.

It looks like the minimum cal frequency resolution is 2x…

Tool/software:

Hi Team,

We have a custom board which is having a clock generator LMK04828.

For that LMK04828, we are feeding 48MHz VCXO. With this configuration, can we generate output clock of 125MHz from LMK04828 ?

If we can…

Tool/software:

Hello,

My customer wants to use CDCM7005 under the following conditions. Is it possible?

   - VCXO_IN = 122.88MHz / PRI_REF = 1 PPS(GPS/IEEE1588) / Output Clock =…

Tool/software:

Hi Team.

We are working on  ADC - DAC Loopback on  FMC Evaluation board, which is having a clock generator - LMK04828 & a transceiver on it.

For this we need a register…

Tool/software:

Hi Team,

Can you please help us with our customer inquiry below.

We are trying to enable CLK_IN_0 (image 1) to have a 10MHz signal sync with the device. Looking at…

Tool/software:

The answer record on the LMK04828: LMK04828 vs LMK04610 post states that the LMK04610, "skew across outputs can be around 100s of ps across…

Tool/software:

Hi,

In the LMK04828 part, three clock inputs (CLKIN0, CLKIN1, OSCIN) are used as inputs in EVAL design. Do we need to use all the three inputs to generate output?

Please find attached image from ADC EVM.

In the…

Tool/software:

Hi team,

Customer met below issue when they evaluated LMK04828, please help to analyze:

• The power is about -14dB when LMK04828 output 1.25GHz to DAC39J84. But after double…

Tool/software:

Hi team,

My customer confirmed the following problem on the LMK04828EVM.

# Configuration
- Used PLL1 and PLL2 in Dual loop mode (VCO=2457.6MHz)
- Phase comparison of PLL1 (datasheet Figure 10. “Phase Detector PLL1…

Tool/software:

I'm using the part 'LMK04828B' in my design. Using TICS tool, i can able to calculate the total power consumption of the IC. But, how to calculate…

Tool/software:

I am trying to achieve a continuous SYSREF signal for debugging my JESD204B links.
The PLL1 isn't locked at the moment, but the PLL2 is sourced from a stable signal generator…

Tool/software:

Hi,
Is there an option to control/configure the LMK04828 Evaluation Board via a Linux OS (W/O using the windows GUI)?

Thanks,
Alon Sechan

Tool/software:

Hi Ti Forum,

I have a JESD based application with the following requirements.

1. Clk_in0 - Not Fixed. It can be anything

2. OSC_in - Connected to 122.88 MHz Crystal with CP0 connection

3. Output Clocks - 100 MHz,…

Tool/software:

Hello,

I have query regarding the PLLatinum simulation.

We are using LMK04828B with external VCXO option in the PLLatinum simulation and have come up with following values for both PLL1 and PLL2 and used the same…

Tool/software:

Hello,

We have an application where the input frequency to LMK04828 is 338 MHz and the output clock is 327 MHz. The observed phase noise performance is shown in RED in below picture. 

e  

We are looking for ways to enhance…