e2e.ti.com/.../am67a-pcie-reference-clock
1 - yes AM67A has several errata items related to PCIe and specifically clocks. I can't say is necessary to use external clock - that is dependent on how you are using PCIe and if the errata items will impact you. But certainly some of the work-arounds for the issue(s) involve using an external refclk.
2 - No in-line capacitor is required. LMK3H0102 can be connected directly to AM67 and PCIe connector/peripheral.

e2e.ti.com/.../am67a-can-the-pcie-subsystem-be-used-with-serdes0-or-only-with-serdes1
Yes, I see that figure 12-121 mention wrongly that the PCIe is supported on SERDES0. It is a mistake; only SERDES1 supports PCIe on AM67.

e2e.ti.com/.../am67a-how-to-generate-pcie-reset

e2e.ti.com/.../am67a-implementing-usb_id-on-a-custom-design

e2e.ti.com/.../am67a-partial-io-peripherals

e2e.ti.com/.../am67a-wkup_uart-mcu_uart-usage

e2e.ti.com/.../faq-tda4vm-dra829v-j721e-how-to-enable-ehrpwm-on-j7-evm-using-linux

e2e.ti.com/.../am67a-is-external-rtc-needed

e2e.ti.com/.../am67a-if-not-using-can-jtag-pins-be-left-as-unterminated-nc

e2e.ti.com/.../am67a-what-is-the-value-of-the-pin-pull-up-and-pull-down-resistors

e2e.ti.com/.../am67a-can-t-the-oldi-pins-be-configured-as-gpio

e2e.ti.com/.../am67a-design-guide-xspi-boot-mode-and-lbclk
I got a response from the ROM expert and he confirmed that OSPI0_LBCLK is not configured or used by ROM, so that particular pin can be used for some other config.
Internal reference clock with Taps that the Boot ROM supports with QSPI, OSPI and XSPI(With PHY disabled) boot modes.
For QSPI and OSPI boot, OSPI0_CLK frequency is 50MHz (Where internal reference clock is 200MHz). ROM has a way of learning the optimal tap settings, which is configured during boot.
While for xSPI boot without PHY, OSPI0_CLK frequency is 25MHz.

e2e.ti.com/.../am67a-can-gb-ethernet-be-operated-on-the-r5f-core
The SDK for AM67A supports the controlling the CPSW ethernet switch from a native Linux driver running on A53.
software-dl.ti.com/jacinto7/esd/processor-sdk-linux-am67a/11_00_00/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Network/CPSW-Ethernet.html
While I did not find specific documentation for AM67A for an example of CPSW Ethernet on R5F core, on AM62P (which also has an R5F core), there are examples of setting up CPSW Ethernet to run on R5F via the MCU+SDK. For example: software-dl.ti.com/.../EXAMPLES_ENET_LWIP_CPSW.html

To my knowledge there is no plan for an MCU+SDK for AM67 so finding examples of Ethernet on R5F directly may not be difficult.

e2e.ti.com/.../am67a-pinctrl-of-gpio-pu-pd-seems-overwritten-when-requesting-the-line-via-gpiod
e2e.ti.com/.../am67a-how-to-connect-the-switch-chip

e2e.ti.com/.../am67a-internal-rgmii-delay

e2e.ti.com/.../am67a-does-am67a-support-four-2mp-30fps-camera-streaming-fish-eye-dewarp-simultaneously

e2e.ti.com/.../am67a-video-audio-requirements-check

e2e.ti.com/.../am67a-are-there-any-differences-between-the-4-csi-camera-ports
www.ti.com/.../spradh2a.pdf

e2e.ti.com/.../faq-am67a-enabling-csi2-sensors-via-fusion-board-on-am6x
e2e.ti.com/.../tda4ven-q1-multi-camera-input-using-mipi-virtual-channel

e2e.ti.com/.../am67a-does-ti-soc-have-plans-to-support-4x8mb-or-1x12mb-camera-sensor-and-usb-3-0

e2e.ti.com/.../am67a-isp-without-lpddr4

e2e.ti.com/.../5692256

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1465462/am67a-could-am67a-isp-support-support-4x8m-cmos-image-sensor

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 2 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 204750 points

Hi Board Designers,

E2E related to PMIC

(+) AM67A: AM67A - Discrete/PMIC power solution - Processors forum - Processors - TI E2E support forums

J722S/AM67x/TDA4VEN/TDA4AEN Processor Automotive Power Designs using TPS6522312-Q1 PMIC
www.ti.com/.../sprt775

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 2 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 204750 points

Hi Board Designers,

E2E related to LPDDR4

(+) TDA4VE-Q1: LPDDR4 design guide what the exact value for the pull up res of ODT? - Processors forum - Processors - TI E2E support forums

e2e.ti.com/.../am67a-lpddr4-routing-topology

e2e.ti.com/.../am67a-lpddr4-layout-recommendatio

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1565555/tda4ven-q1-layout-questions-about-lpddr4-in-evm

(+) AM67A: How user can set Drive strength/Termination for DDR_CK - Processors forum - Processors - TI E2E support forums

The reason we use 33-ohm SE/66-ohm DIFF in pace of 40-ohm SE/80-ohm DIFF is because of the T-branch segments on the PCB. When the trace splits into two segments, to maintain the same impedance seen by the source, the impedance should double. So a 40-ohm SE trace would become two 80-ohm SE traces. 80-ohms SE trace are typically not achievable on a PCB. 66-ohms SE may not be achievable either but is much closer than 800hms SE. So the 33-ohm SE/66-ohm DIF might give you better signal integrity. Each PCB design is different and is up to each customer to simulation and determine best implementation for their design.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 2 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 204750 points

Hi Board Designers,

FYI

(+) AM67A: Request for Guidance on C7x Core Software Development (AM67A) - Processors forum - Processors - TI E2E support forums

AM67A: Request for Guidance on C7x Core Software Development (AM67A)

Please note that TI doesn`t support Beagle Y AI platform on TI E2E forums. Currently AM67A product is designed for C7x DSP to be used as DL compute accelerators. There is currently no roadmap available to enable C7x to be used as a DSP compute accelerator rather than DL accelerator. I am looping in relevant expert from productline who can indicate if there is future plan to support the platform and offer C7x DSP development option on this platform or if they can provide information for partners who may be able to support you outside of the TI standard offering to port/develop code on this platform.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 2 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 204750 points

Hi Board Designers,

Inputs related to IBIS-AMI model availability

(+) AM67A: IBIS-AMI model request - Processors forum - Processors - TI E2E support forums

AM67A: IBIS-AMI model request

I understand that the IBIS-AMI models are shared under NDA.

Please reach out to the filed team you are working to take this forward.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 1 month ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 204750 points

Hi Board designers,

Inputs regarding weight and material content

https://www.ti.com/materialcontent/home

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 1 month ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 204750 points

Hi Board designers,

Inputs regarding Package shelf life

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1520415/am625-package-shelf-life

Please refer below links

https://www.ti.com/support-quality/quality-policies-procedures/product-shelf-life.html

https://www.ti.com/support-quality/faqs/product-shelf-life-faqs.html

https://www.ti.com/packaging/docs/mslsearch.tsp?OPN=AM6254BTGFHIAMCRQ1&searchSelected=devpartno&searchkey=AM625#divline

https://www.ti.com/support-quality/reliability/reliability-home.html

https://www.ti.com/lit/an/spraby1a/spraby1a.pdf

https://www.ti.com/lit/pdf/snoa550

https://www.ti.com/lit/an/slva840/slva840.pdf

/cfs-file/__key/communityserver-discussions-components-files/791/Baking-Procedure.pdf

(+) AM62P: Air Humidity for Storage and Operation - Processors forum - Processors - TI E2E support forums

I got the ask from a customer if we define the storage air humidity and the air humidity in operation for the AM62P?

I guess not, but I wanted to double check with you.

Also, this is the requirements they are asking for:

Storage air humidity: 30% to 95% RH
Air humidity in operation: 30% to 95% RH

Prior to board assembly but removed from sealed packaging -> device is specified as MSL3, rated for 168hrs exposure at ≤30°C/60%RH ambient conditions without a re-bake being required before board assembly.

We have no spec for operational humidity specification, but device completed and passed relevant qualification at MSL3 moisture precondition + 1000hrs 85°C/85%RH THB (Temperature, Humidity, Bias) per standard JEDEC test conditions

Regards,

Sreenivasa