Tool/software:
Hi TI Experts,
I am working on a design using OMAP-L138 processor plus DSP.
Checking if you have some recommendations to follow?
Hi Board Designers,
Please refer below:
Support
References
L138
https://www.ti.com/product/OMAP-L138
Data Sheet
https://www.ti.com/lit/ds/symlink/omap-l138.pdf
TRM
https://www.ti.com/lit/ug/spruh77c/spruh77c.pdf
Errata
https://www.ti.com/lit/er/sprz301m/sprz301m.pdf
Schematics review checklist
https://www.ti.com/lit/an/sprack9/sprack9.pdf
Reference
TMS320C6748
https://www.ti.com/product/TMS320C6748
Data Sheet
https://www.ti.com/lit/gpn/tms320c6748
https://www.ti.com/lit/ds/symlink/tms320c6748.pdf
Schematics review checklist
https://www.ti.com/lit/an/sprack9/sprack9.pdf
Data sheet reference
3.8 Terminal Functions
3.8.7 Serial Peripheral Interface Modules (SPI)
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up, an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the Device Configuration section. For electrical specifications on pullup and internal pulldown circuits, see the Device Operating Conditions section.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C.
3.8.26 Reserved and No Connect
3.8.27 Supply and Ground Table
3-31. Supply and Ground Terminal Functions
3.9 Unused Pin Configurations
Table 3-32. Unused USB0 and USB1 Signal Configurations
Table 3-34. Unused RTC Signal Configuration
5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
6 Peripheral Information and Electrical Specifications
6.5 Crystal Oscillator or External Clock Input
6.6 Clock PLLs
Figure 6-8. PLL External Filtering Components
6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)
Table 6-5. Maximum Internal Clock Frequencies at Each Voltage Operating Point
6.10 External Memory Interface A (EMIFA)
6.11 DDR2/mDDR Memory Controller
Figure 6-18. DDR2/mDDR Single-Memory High Level Schematic
6.11.3.6 Bulk Bypass Capacitors
6.11.3.7 High-Speed Bypass Capacitors
6.32 General-Purpose Input/Output (GPIO)
TRM Reference
OSCIN
System Configuration (SYSCFG) Module
11.5.23 Pullup/Pulldown Enable Register (PUPD_ENA)
The pullup/pulldown enable register (PUPD_ENA) enables the pull-up or pull-down functionality for the pin group n defined in your device-specific data manual. The PUPD_ENA is shown in Figure 11-50 and described in Table 11-54. Figure 11-50. Pullup/Pulldown Enable Register (PUPD_ENA)
11.5.24 Pullup/Pulldown Select Register (PUPD_SEL)
The pullup/pulldown select register (PUPD_SEL) selects between the pull-up or pull-down functionality for the pin group n defined in your device-specific data manual. The PUPD_SEL is shown in Figure 11-51 and described in Table 11-55 and Table 11-56.
Chapter 21
General-Purpose Input/Output (GPIO)
21.3.3 GPIO Direction Registers (DIRn)
The GPIO direction register (DIRn) determines if GPIO pin j in GPIO bank k is an input or an output. Each of the GPIO banks may have up to 16 GPIO pins. By default, all the GPIO pins are configured as inputs (bit value = 1). The GPIO direction register (DIR01) is shown in Figure 21-4, DIR23 is shown in Figure 21- 5, DIR45 is shown in Figure 21-6, DIR67 is shown in Figure 21-7, DIR8 is shown in Figure 21-8, and described in Table 21-5. See Table 21-1 to determine the DIRn bit associated with each GPIO bank and pin number.
21.3.4 GPIO Output Data Registers (OUT_DATAn)
The GPIO output data register (OUT_DATAn) determines the value driven on the corresponding GPIO pin j in GPIO bank k, if the pin is configured as an output (DIRn = 0). Writes do not affect pins not configured as GPIO outputs. The bits in OUT_DATAn are set or cleared by writing directly to this register. A read of OUT_DATAn returns the value of the register not the value at the pin (that might be configured as an input). The GPIO output data register (OUT_DATA01) is shown in Figure 21-9, OUT_DATA23 is shown in Figure 21-10, OUT_DATA45 is shown in Figure 21-11, OUT_DATA67 is shown in Figure 21-12, OUT_DATA8 is shown in Figure 21-13, and described in Table 21-6. See Table 21-1 to determine the OUT_DATAn bit associated with each GPIO bank and pin number.
Chapter 23 Inter-Integrated Circuit (I2C) Module
23.2.4 Signal Descriptions
The I2C peripheral has a serial data pin (I2Cx_SDA) and a serial clock pin (I2Cx_SCL) for data communication, as shown in Figure 25-1. These two pins carry information between the device and other devices that are connected to the I2C-bus. The I2Cx_SDA and I2Cx_SCL pins both are bi-directional. They each must be connected to a positive supply voltage using a pull-up resistor. When the bus is free, both pins are high. The driver of these two pins has an open-drain configuration to perform the required wired-AND function. See your device-specific data manual for additional timing and electrical specifications for these pins.
23.2.4.1 Input and Output Voltage Levels The master device generates one clock pulse for each data bit that is transferred. Due to a variety of different technology devices that can be connected to the I2C-bus, the levels of logic 0 (low) and logic 1 (high) are not fixed and depend on the associated power supply level. See your device-specific data manual for more information.
Schematics review checklist reference
2.4.8 USB
2.4.8.1 USB0 (USB 2.0 OTG)
Collaterals for reference
BeagleBoard-xM
https://git.beagleboard.org/beagleboard/beagleboard-xm/-/blob/master/BeagleBoard-xM_SCH.pdf
TMDSLCDK138 Development kit | TI.com
OMAP-L138 Power Consumption Summary
https://www.tij.co.jp/jp/lit/an/sprabg0/sprabg0.pdf
Schematics
https://www.mouser.com/datasheet/2/383/EVMOMAPL137_TechRef_revg-240.pdf
Powering the OMAP-L132/OMAP-L137/OMAP-L138 Processors with the TPS650061 Power Management IC
https://www.ti.com/lit/an/slva513/slva513.pdf
TPS65950 Schematic Checklist
https://www.ti.com/lit/an/swca073b/swca073b.pdf
Using the OMAP-L132/L138 Bootloader
https://www.ti.com/lit/an/sprab41f/sprab41f.pdf
Programming mDDR/DDR2 EMIF on OMAP-L1x/C674x
https://www.ti.com/lit/an/spracq4/spracq4.pdf
TMS320C674x/OMAP-L1x Processor Peripherals Overview
https://www.ti.com/lit/ug/sprufk9f/sprufk9f.pdf
OMAP-L138 Low Cost Development Kit
https://www.ti.com/lit/ug/tiduam7/tiduam7.pdf
OMAP-L138 Applications Processor System Reference Guide
/cfs-file/__key/communityserver-discussions-components-files/791/0677.OMAP-L138-Reference-guide.pdf
OMAP-L1x Software Solutions
https://www.tij.co.jp/jp/lit/ml/sprt529b/sprt529b.pdf?
https://script.spoken-tutorial.org/index.php/Low_Cost_Access_Device#HawkBoard
Additional
TMS320C6412 Hardware Designer’s Resource Guide
F2812 PGF IBIS Model CLK is NC signals
E2E
Please refer to the document attached for full Debug and Trace capabilities available on the device.
Debug and Trace Capabilities on OMAPL1X_AM1x_DA8x devices - Texas Instruments Wiki.pdf
The only open-drain IOs are the I2C signals and they are open-drain ONLY when configured as I2C functions. Otherwise, they are normal totem-pole CMOS outputs.
I checked a couple of other IBIS files available on TI.com, and they also do not provide model data for the oscillator inputs (even if used as an clock input from some LVCMOS oscillator source instead of a crystal).
I suspect the reason is because these clock/crystal inputs are analog in nature, but I will follow up with our IBIS expert. IBIS files are meant for IO buffers.
This NC for OSCIN/CLKIN pins is consistent with other devices.
We checked with our Design team on this and got the following reply:
"We do not provide IBIS models for power/ground/Oscillator pins. Usually SI simulations are significant for drivers. X1 being a receiver may be modeled as a simple cap".
Just to clarify further, SI simulations are significant primarily for drivers. i.e. Signal integrity simulations are useful only for I/O pins and not for input-only, clocking pins like X1.
OMAP-L138: OSCIN (pin L19) missing in IBIS model?
OSCIN input (pin L19) is missing in OMAP-L138 IBIS model. Do we have updated IBIS file?
Or is OSCIN not required for IBIS? Having said this should customer try to find an option on his compilation tools to ignore these pins…
Generally speaking, OSC inputs are not simulated, especially if an actual crystal is used. IBIS does not simulate analog inputs.
Regards,
Sreenivasa
Hi Board Designers,
Inputs related to configuring SPI for master or slave
Questions
The names of the signals provided the connectivity details:
SOMI (Slave Out, Master In) of the slave device should be connected to SOMI of the Master device.
SIMO (Slave In, Master Out) of the slave device should be connected to SIMO of the Master device.
Serial Peripheral Interface (SPI)
NOTE: The value x indicates the applicable SPI; that is, SPI0, SPI1, etc. See your device-specific data manual to determine how many SPIs are available on your device. The value n indicates the SPI pins available. See your device-specific data manual to determine how many SPI pins are available on your device. A Indicates the log controlled by SPI register bits.
B Solid line represents data flow for SPI master mode. Dashed line represents data flow for SPI slave mode.
In master mode, SIMO is an output pin and SOMI is the input pin.
In slave mode, SIMO is an input pin and SOMI is an output pin.
L138 <-> L138 should work as long as the IPs are configured in the correct mode by software, one Master, and one Slave. The correct CS also needs to be setup.
Should be easy enough to probe for the expected activity on the clock, data, and CS to determine what is not correct.
Should be fine for low speed testing.
Regards,
Sreenivasa
Hi Board Designer,
Refer inputs related to Advisory 2.3.18
(+) TMS320C6747: EVM documentation - Processors forum - Processors - TI E2E support forums
L137 EVM documentation for reference
My customer is interested in evaluating C6747.
He found below EVM on TI.com.
https://www.ti.com/tool/TMDSOSKL137
But there is no user’s guide nor schematics are available.
Where can I found such technical documents?
(+) Power management forum - Power management forum - Power management - TI E2E support forums
I found the cause of the problem.
It was caused by the rise of the DC stabilized power supply input to this device.
24Vin---DCDC5V---DCDC1.2V
|-DCDC1.8V
|-DCDC3.3V
When 24Vin had a poor rise time, the rise time of DCDC5V was also poor, and a leakage occurred at 1.8V as 3.3V rose after 1.8V stabilized.
When DCDC5V was changed to a device with good rise time, it rose normally.
This issue has been observed on multiple boards.
And the customer tried an A-B-A swap and they found that the issue depends on the power-up sequence (The raising time of 3.3V).
Could you confirm the following figure?
This phenomen seems to exact matches to Errata Advisory 2.3.18 for TMS320C6748.
We found that this issue seems to be resolved by dealing with one of the following three.
- Shorten the raising time of 3.3V from 4.3ms to 610us
- Disconnect 3.3V power from dual voltage IOs
- Add large load capacitor on the 1.8V power line
(25) TMS320C6748 power supply problems - Processors forum - Processors - TI E2E support forums
The problems got exacerbated as we had a load switch to switch the 3.3V rail to the DSP. This load switch has got two internal switches, one to switch the rail when turned on and the other to drain the rail when switched off. When sequencing the 1.2V and 1.8V rails this switch ( the draining switch) would sink current via the 3.3V rail and not allow the 3.3V rail to ramp properly especially during the 1.8V ramp.
We solved the problem today by using a P-channel mosfet instead of the load switch.
We have now ordered another load switch from TI without the output draining switch.
Can you confirm such an issue?
It seems something related to 3.3V-1.8V is describe on the specification, could it be link to their issue?
The issue seems like the leakage that we already addressed in the Advisory 2.3.18 in C6746 errata.
www.ti.com/.../sprz304h.pdf
Please refer to this and try to implement one of the workaround to avoid this leakage.
customer was able to fix the issue based on silicon errata.
In reality, there is no ramp up time requirement available for any of the supply rail during power on sequence. However you should be adhere to the power on sequence, the recommendation is to power on the next rail after the first rail reaches its nominal value.
In order to avoid the issue discussed in errata Advisory 2.3.18, you are required to add certain bulk capacitance to generate the load current of 140mA during the power supply ramp. The table 12 shows the ramp time of DVDD3318 rail for various value of bulk capacitance. This ramp time is solely depends on the capacitance value and there is no requirement on this again
Regards,
Sreenivasa
